Semiconductor Structure With Region-Specific CESL Thickness Control
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Solution Overview
Problem
The increasing density and reduced dimensions of integrated circuits in the semiconductor industry make it challenging to adjust component characteristics, particularly in managing parasitic resistance and capacitance across devices with different metal dimensions.
Innovation Solution
The solution involves forming semiconductor structures with defined regions having different spacer layer and contact etching stop layer thicknesses, allowing for controlled parasitic resistance and capacitance by varying the thickness of these layers in specific regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the density of integrated circuits is increased and dimensions are reduced, then more components can be integrated into a given area, but it becomes difficult to adjust component characteristics such as parasitic resistance and capacitance among devices with different metal dimensions
Solution Approach 1:
The patent applies local quality by forming different thicknesses of contact etching stop layers and spacer layers in different regions of the semiconductor device. Specifically, a first contact etching stop layer with a first thickness is formed in a first region, and a second contact etching stop layer with a second thickness (different from the first) is formed in a second region. This allows each region to have optimized component characteristics (parasitic resistance and capacitance) tailored to its specific metal dimensions and performance requirements, thereby maintaining adaptability of component characteristics while achieving high integration density
2Productivity
If devices with different metal dimensions are fabricated on the same substrate, then integration density increases, but parasitic resistance and capacitance cannot be optimized for each device type
Solution Approach 1:
The patent implements local quality by creating region-specific layer thicknesses: a first region contains a contact etching stop layer with a first thickness and a spacer layer with a first thickness, while a second region contains a contact etching stop layer with a second thickness and a spacer layer with a second thickness. This enables each region to be optimized for its specific device type and metal dimensions, allowing parasitic resistance and capacitance to be controlled and optimized for each device while maintaining high integration density on the same substrate
Solution Approach 2:
The patent applies segmentation by dividing the semiconductor substrate into multiple regions (first region and second region), each with independently optimized layer structures. The contact etching stop layers and spacer layers are segmented into different thicknesses for different regions, allowing each segment to be optimized for its specific performance requirements. This segmentation strategy enables simultaneous optimization of parasitic characteristics for multiple device types while achieving high integration density
Data Source
AI summary
A semiconductor structure includes a first semiconductor device formed over a substrate. The first semiconductor device includes a first source/drain feature over the substrate, a first gate structure over the substrate, a first conductive feature over the first source/drain feature, and a first insulation layer between the first gate structure and the first conductive feature, wherein the first insulation layer comprises a first contact etching stop layer (CESL) in contact with the first source/drain feature. The semiconductor structure includes a second semiconductor device formed over the substrate, including a second source/drain feature over the substrate, a second gate structure over the substrate, a second conductive feature over the second source/drain feature, and a second insulation layer between the second gate structure and the second conductive feature, the second insulation layer comprises a second CESL in contact with the second source/drain feature, wherein a thickness of the first CESL is less than a thickness of the second CESL.