Semiconductor Package Chamfered Cavity Sidewall Nozzle Collision
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Solution Overview
Problem
Semiconductor packages face defects during the mounting process due to interference between the nozzle and the package structure, particularly when handling small electronic components, leading to alignment issues and difficulties in smoothly supplying the resin for encapsulation.
Innovation Solution
The semiconductor package design includes a support member with a chamfered upper region in its sidewall structure, which extends the upper space of the cavity, reducing the likelihood of collision with the nozzle and allowing for stable encapsulation of electronic components, thereby preventing defects and ensuring smooth resin supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard vertical sidewall structure is used in the support member cavity, then the package structure is simple and easy to manufacture, but the nozzle may collide with the sidewall during mounting of small electronic components causing alignment defects
Solution Approach 1:
The chamfered upper region is formed in advance on the sidewall structure before the mounting process. This preliminary geometric modification creates additional clearance space that prevents nozzle collision during subsequent component placement operations, thereby improving mounting reliability without requiring complex active control systems.
Solution Approach 2:
The solution transitions from a simple vertical sidewall (one-dimensional height variation) to a chamfered sidewall that introduces radial dimension changes. The chamfer creates an angled surface that extends the effective mounting space outward, providing the nozzle with additional clearance in the radial direction to avoid collision with the vertical sidewall.
2Ease of manufacture
If the cavity upper space is limited by a vertical sidewall, then the package structure is compact, but the resin for encapsulant cannot be smoothly supplied to all regions
Solution Approach 1:
The chamfered upper region is pre-formed on the sidewall to create an expanded upper space configuration before resin injection. This preliminary geometric preparation ensures that resin can flow smoothly into all cavity regions including corners and edges, preventing voids and ensuring complete encapsulation without requiring complex injection molding adjustments.
Solution Approach 2:
The chamfered sidewall structure adds radial dimension to the cavity upper space, transforming it from a simple vertical cylinder to a shape with extended upper regions. This dimensional change creates better resin flow pathways and eliminates dead zones where resin might stagnate, improving manufacturability while accepting a moderate volume increase.
3Manufacturing precision
If the sidewall structure is modified with a chamfered upper region, then alignment defects are prevented and resin supply is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The chamfered upper region is incorporated into the support member manufacturing process itself, forming the precise geometric feature before assembly. This preliminary formation of the chamfered geometry ensures consistent alignment precision for subsequent component mounting while consolidating the precision requirement into a single manufacturing step rather than requiring multiple adjustment operations.
Solution Approach 2:
The solution changes the geometric parameters of the sidewall from a simple vertical profile to a chamfered profile with specific angle and dimension parameters. By optimizing these geometric parameters (chamfer angle, width, position), the design achieves improved alignment precision and resin flow characteristics while keeping the manufacturing process relatively straightforward through standard machining or molding operations.
Data Source
AI summary
A semiconductor package includes: a connection member having first and second surfaces opposing each other and including a redistribution layer; a support member disposed on the first surface of the connection member, including a cavity, and having an inner sidewall surrounding the cavity of which an upper region is chamfered; a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the redistribution layer; at least one electronic component disposed between the semiconductor chip and the inner sidewall and having connection terminals electrically connected to the redistribution layer; and an encapsulant encapsulating the semiconductor chip and the at least one electronic component disposed in the cavity.