3D Semiconductor Channel Annealing for Interface Defect Reduction
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Solution Overview
Problem
The channel carrier mobility in three-dimensional semiconductor devices is reduced due to surface roughness and interface state defects caused by the growth temperature of oxide layers and native oxide thinning during the formation of polycrystalline silicon channel layers, leading to decreased memory cell reliability.
Innovation Solution
A method involving the formation of a dummy channel sacrificial layer and a buffer layer on the channel surfaces, followed by annealing treatments in specific gas atmospheres to reduce surface roughness and interface state defects, improving channel carrier mobility and memory cell reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If oxide layers are grown at high temperature during polycrystalline silicon channel layer formation, then good bottom contact characteristics are achieved, but surface roughness increases and interface state defects are generated
Solution Approach 1:
A buffer layer is formed on the channel layer surface before the oxide layer deposition. This preliminary action prepares a smooth interface that prevents the generation of interface state defects during subsequent high-temperature oxide growth, while still allowing good bottom contact characteristics to be achieved.
Solution Approach 2:
The buffer layer acts as an intermediary between the channel layer and the oxide layer. It mediates the interaction by providing a smooth interface that reduces surface roughness and interface state defects, while still permitting effective bottom contact formation during device operation.
2Reliability
If native oxide is thinned to improve interface quality, then interface state defects are reduced, but surface roughness increases
Solution Approach 1:
The buffer layer serves as an intermediary that replaces the need for native oxide thinning. It provides a smooth interface directly on the channel layer, eliminating interface state defects without causing surface roughness issues that would result from aggressive oxide removal processes.
Solution Approach 2:
Instead of changing the physical state of the native oxide through thinning, the invention introduces a buffer layer with optimized material properties and thickness parameters. This changes the interface characteristics from a damaged rough surface to a controlled smooth interface, simultaneously improving both interface quality and surface finish.
3Ease of manufacture
If polycrystalline silicon channel layer is formed with simple process, then manufacturing ease is improved, but channel carrier mobility decreases due to grain boundary gaps
Solution Approach 1:
The invention introduces a buffer layer with specific material composition and thickness parameters that passivate grain boundary gaps in the polycrystalline silicon channel layer. This parameter optimization maintains the simplicity of the polycrystalline silicon formation process while significantly improving channel carrier mobility by reducing defect states at grain boundaries.
Solution Approach 2:
The channel structure becomes a composite of the polycrystalline silicon channel layer and the buffer layer. The buffer layer component addresses the grain boundary gap issue in the polycrystalline silicon, improving carrier mobility while maintaining the manufacturing advantages of using polycrystalline silicon instead of single crystal materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of a dummy channel sacrificial layer and buffer layer, combined with annealing treatments, effectively reduces interface state defects and surface roughness, enhancing channel carrier mobility and memory cell reliability in three-dimensional semiconductor devices.
Implementation Method 1
performing annealing treatment to at least one surface of the channel layers to reduce the surface roughness and the interface state
Data Source
AI summary
A method of manufacturing three-dimensional semiconductor device includes the steps of: forming a stack structure of a plurality of a first material layers and a second material layers on a substrate in the memory cell region; etching the stack structure to form a plurality of trenches; forming channel layers in the plurality of trenches; and reducing the surface roughness and the interface state by performing annealing treatment to at least one surface of the channel layers.