Semiconductor Channel Capping Layer Oxidation for High-k Dielectric Integration
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Solution Overview
Problem
As critical dimensions shrink in semiconductor devices, conventional gate insulator materials like silicon dioxide exhibit excessive leakage current, and high-k dielectrics, while improving insulating properties, suffer from charge scattering and charge trapping issues that degrade transistor performance, especially at the 45 nm technology node and beyond.
Innovation Solution
A silicon-comprising channel capping layer is oxidized and interposed between the channel and a high-k dielectric gate insulator, effectively burying the channel and reducing undesirable interfacial effects such as charge scattering and trapping, allowing for the use of metal gate electrodes with high-k dielectrics in advanced devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If high-k dielectrics are used as gate insulators, then leakage current is reduced, but charge scattering and charge trapping occur that degrade transistor performance
Solution Approach 1:
A silicon-containing capping layer is introduced as an intermediary between the channel and the high-k dielectric gate insulator. This intermediate layer prevents direct interaction between the channel and high-k material, eliminating charge scattering and trapping at the interface while preserving the low leakage current benefits of the high-k dielectric.
Solution Approach 2:
The gate insulator structure is segmented into multiple layers: a conventional gate dielectric layer adjacent to the channel, and a high-k dielectric layer positioned over the capping layer. This segmentation allows the channel to interact with the reliable conventional dielectric while the high-k layer provides enhanced insulation, dividing the functions to resolve the contradiction.
2Length of moving object
If the channel is placed in close proximity to the high-k gate dielectric, then device scaling is achieved, but charge trapping and coulomb scattering increase
Solution Approach 1:
The silicon-containing capping layer serves as a protective intermediary that physically separates the channel from the high-k dielectric. This intermediary layer prevents charge trapping and coulomb scattering while allowing the device to maintain scaled dimensions, as the capping layer is thin enough not to significantly increase the overall device footprint.
3Loss of energy
If metal gate electrodes are used with high-k dielectrics, then insulating properties are improved, but oxide reduction occurs that decreases insulating properties
Solution Approach 1:
The silicon-containing capping layer acts as a protective intermediary between the metal gate electrode and the high-k dielectric oxide. This intermediate layer prevents direct reduction of the oxide by the metal gate, preserving the insulating properties of both materials while allowing their beneficial combination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances carrier mobility and drive current while stabilizing the threshold voltage, enabling the use of high-k dielectrics with metal gates in high-performance devices suitable for the 45 nm node and beyond, improving device performance and scalability.
Implementation Method 1
oxidizing the first surface of the channel capping layer
Data Source
AI summary
Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer.