Semiconductor Channel Depth Control for Integration
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Solution Overview
Problem
The increased demand for highly integrated semiconductor devices poses fabrication challenges due to reduced process margins in exposure processes, making it difficult to achieve finer patterns and higher speeds in semiconductor devices.
Innovation Solution
The method involves forming impurity regions of different conductivity types at specific depths in a substrate to create channel regions for both buried channel array transistors and planar transistors, allowing for the formation of device isolation layers and gate electrodes without a mask, simplifying the fabrication process while maintaining device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If exposure processes are used to define fine patterns for highly integrated semiconductor devices, then integration level increases, but process margins are reduced making fabrication more difficult
Solution Approach 1:
The substrate is divided into cell region and peripheral region, with separate impurity implantation processes for each region. This segmentation allows independent optimization of fabrication parameters for high-speed cell transistors and peripheral transistors, enabling high integration while maintaining adequate process margins through region-specific control
Solution Approach 2:
Different impurity concentrations and depths are applied to different regions: the cell region receives first impurity at a first depth for high-speed operation, while the peripheral region receives second impurity at a second depth for stable characteristics. This local differentiation allows each region to operate at optimal performance points without compromising overall device integration
2Reliability
If impurity implantation is performed at different depths for cell and peripheral regions, then device characteristics are optimized, but fabrication process complexity increases
Solution Approach 1:
The solution moves from two-dimensional planar processing to three-dimensional depth control by implanting impurities at different target depths (first depth for cell region, second depth for peripheral region). This vertical dimension differentiation allows optimization of device characteristics through depth-controlled doping while maintaining a unified fabrication flow, reducing the perceived process complexity
Solution Approach 2:
The invention changes the implantation parameters (impurity type, concentration, and target depth) according to the specific requirements of each region. By systematically varying these parameters rather than using fixed processes, the method optimizes device characteristics while providing a structured approach that manages fabrication complexity through parameter optimization rather than process multiplication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient fabrication of semiconductor devices with improved integration and speed by forming impurity regions at precise depths, enhancing the formation of channel regions for both types of transistors, thus addressing the challenges of reduced process margins and increased integration demands.
Implementation Method 1
forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth
Data Source
AI summary
Methods of fabricating semiconductor devices include forming a first impurity region in a substrate by implanting a first impurity of a first conductivity type in a cell region and a peripheral region of the substrate to a first target depth from a top surface of the substrate; forming a second impurity region in the cell region and the peripheral region by implanting a second impurity of the first conductivity type into the cell region and the peripheral region to a second target depth that is smaller than the first depth from the top surface of the substrate; forming a cell transistor with a channel in the cell region, wherein the first impurity region forms the channel of the cell transistor; and forming a peripheral transistor with a channel in the peripheral region, wherein the second impurity region forms the channel of the peripheral transistor.