Semiconductor Channel Layer Layout for Precise DRAM Channel Length
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Solution Overview
Problem
DRAM manufacturers face challenges in shrinking memory cell area due to shrinking word line spacing, which affects the miniaturization and complexity of integrated circuits, and existing technologies struggle to precisely control the channel length in semiconductor devices.
Innovation Solution
A semiconductor device and manufacturing method involving a semiconductor layer with doped regions, where the channel length is determined by the vertical length of a word line, and doped regions are formed in one wafer to be bonded with another wafer containing gate structures, allowing for precise control without considering the thermal budget of the other wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If word line spacing is shrunk to reduce memory cell area, then memory cell area is reduced, but channel length control precision deteriorates
Solution Approach 1:
The invention divides the semiconductor device into two separate wafers: one containing the semiconductor layer with doped regions, and another containing the gate structure with word lines. This segmentation allows independent optimization of each wafer's features, enabling precise channel length control through the bonded interface while maintaining reduced memory cell area through compact word line spacing in the gate wafer.
Solution Approach 2:
The invention introduces a bonding interface between two separate wafers as an intermediary mechanism. This bonding interface serves as a precise reference plane that enables accurate alignment and definition of channel length, decoupling the channel length control from the word line spacing constraints. The bonding process creates a stable reference that allows independent scaling of word line spacing without compromising channel length precision.
2Ease of manufacture
If doped regions are formed in one wafer bonded to another wafer with gate structures, then manufacturing flexibility and channel length control are improved, but device complexity increases
Solution Approach 1:
The invention segments the manufacturing process into two independent wafer fabrication sequences that can be optimized separately. One wafer is dedicated to forming the semiconductor layer and doped regions with their specific thermal budget requirements, while the other wafer is dedicated to forming the gate structures and word lines. This segmentation allows each process to be optimized independently, improving ease of manufacture despite the added complexity of wafer bonding.
Data Source
AI summary
A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bit line, a semiconductor layer, and a word line. The bit line is disposed over the substrate. The semiconductor layer is disposed over the bit line. The word line abuts the semiconductor layer. The word line has a lower surface facing the substrate and an upper surface opposite to the lower surface. The semiconductor layer includes a first doped region with a first conductive type, a second doped region with a second conductive type opposite to the first conductive type. The first doped region is disposed between the second doped region and the bit line. The first boundary between the first doped region and the second doped region is substantially aligned with the lower surface of the word line.