Semiconductor Device Channel Hole Alignment via Segmented Stacks
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Solution Overview
Problem
The integration density of nonvolatile memory devices is limited by the area occupied by unit memory cells, and there is a need to reduce misalignment in channel holes between the lower and upper stack structures in three-dimensional memory devices to enhance reliability.
Innovation Solution
A semiconductor device design that includes a first and second stack structure with gate electrodes stacked sequentially, a junction layer, and interlayer insulating layers, where the channel holes are formed to penetrate through these structures, reducing misalignment by varying the width and height of channel hole portions, thereby improving integration density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If channel holes are formed to penetrate through both lower and upper stack structures, then integration density is improved, but misalignment between channel hole portions occurs reducing reliability
Solution Approach 1:
The channel hole is divided into multiple distinct portions: a first portion penetrating the lower stack structure, a second portion extending through the junction layer, and a third portion penetrating the upper stack structure. This segmentation allows each portion to be independently formed and controlled, ensuring proper alignment between the lower and upper stack structures while maintaining high integration density.
Solution Approach 2:
Different portions of the channel hole are formed with different characteristics tailored to their specific functions. The first portion is optimized for penetrating the lower stack structure, the second portion is designed with specific width and depth for junction layer penetration, and the third portion is optimized for the upper stack structure. This local optimization ensures both high integration density and reliable alignment.
2Area of stationary object
If three-dimensional memory device structure is implemented, then area occupation is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a three-dimensional memory device structure where stack structures are vertically stacked to extend into the depth dimension. This vertical stacking allows high integration density to be achieved without increasing the planar occupied area. The channel holes are formed to penetrate through multiple vertical layers, utilizing the third dimension (depth) to increase storage capacity while maintaining a compact footprint.
Solution Approach 2:
The three-dimensional structure is segmented into distinct lower and upper stack structures connected by junction layers. This segmentation allows each stack structure to be independently formed and aligned, reducing the overall manufacturing precision requirements compared to forming a single continuous structure, while still achieving high integration density through vertical stacking.
Data Source
AI summary
A semiconductor device includes a first substrate in which a first region and a second region are defined, a first stack structure with first gate electrodes displaced and stacked sequentially on the first substrate, a second stack structure with second gate electrodes displaced and stacked sequentially on the first stack structure, a junction layer disposed between the first stack structure and the second stack structure, a first interlayer insulating layer disposed on a side surface of the first stack structure, a second interlayer insulating layer covering the second stack structure, a first channel hole that penetrates through structure(s) and/or layer(s) and a second channel hole that penetrates through structure(s) and/or layer(s). A height of the second portion of the first channel hole in a second direction orthogonal to the first direction is less than a height of the second portion of the second channel hole in the second direction.