Neural Network Alignment Verification for Semiconductor Channel Structures
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Solution Overview
Problem
The increasing height of structures in semiconductor devices perpendicular to the substrate leads to alignment issues between upper and lower channel structures, affecting the reliability and electrical characteristics of the devices, as existing methods fail to accurately verify and correct these alignments.
Innovation Solution
A method involving the formation of lower and upper molds with channel structures, removal of the upper mold to capture images, and the use of a neural network to reconstruct and compare cross-sections of channel structures, ensuring accurate alignment verification between the upper and lower structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If structures are extended in the perpendicular direction to increase integration degree, then the degree of integration is improved, but alignment accuracy between upper and lower structures deteriorates
Solution Approach 1:
The patent applies preliminary action by forming alignment marks and reference structures on the substrate before forming the lower and upper channel structures. This pre-established reference system enables accurate alignment verification throughout the manufacturing process, preventing alignment deterioration that would otherwise occur with increased structural height and complexity.
Solution Approach 2:
The patent implements feedback mechanisms through multiple verification steps including forming alignment marks, capturing images of the lower mold and upper channel structures, comparing their positions, and adjusting subsequent formation processes based on detected alignment deviations. This closed-loop feedback ensures alignment accuracy is maintained even as integration degree increases.
2Adaptability or versatility
If multiple operations are used to form divided structures, then the degree of integration is improved, but alignment reliability deteriorates
Solution Approach 1:
The patent forms alignment marks and reference structures before dividing the channel structures into lower and upper portions through multiple operations. This preliminary alignment framework remains consistent throughout subsequent division operations, ensuring that each divided structure can be accurately positioned and verified for proper alignment.
Solution Approach 2:
The patent incorporates feedback verification at each stage of the multiple operations by capturing images, comparing positions between lower mold and upper channel structures, and adjusting processes based on detected alignment states. This continuous feedback maintains reliability despite the increased number of operational steps required for high integration.
3Device complexity
If alignment verification methods are not improved, then manufacturing complexity is reduced, but measurement precision of alignment state deteriorates
Solution Approach 1:
The patent introduces alignment marks and reference structures as intermediary elements that facilitate precise alignment verification. These intermediaries serve as measurable references between the lower and upper channel structures, enabling accurate measurement without significantly increasing overall manufacturing complexity.
Solution Approach 2:
The patent uses image capture and digital comparison to create copies of the alignment state for analysis. By capturing images of the lower mold and upper channel structures and comparing their digital representations, the system achieves high measurement precision through optical copying and computational analysis rather than complex physical measurement apparatus.
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a lower mold having lower layers stacked on a substrate and lower channel structures passing therethrough; forming an upper mold including upper layers stacked on the lower mold and upper channel structures passing therethrough; removing the upper mold to expose an upper surface of the lower mold; separating an upper original image in which traces of the upper channel structures are displayed, and a lower original image in which the lower channel structures are displayed, from an original image capturing the upper surface of the lower mold; inputting the upper original image into a learned neural network to acquire an upper restored image in which cross sections of the upper channel structures are displayed; and comparing the upper restored image with the lower original image to verify an alignment state of the upper and lower molds.