Semiconductor Channel Pattern With Selective Epitaxial Growth
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Solution Overview
Problem
Highly integrated semiconductor devices face challenges in maintaining optimal operating characteristics due to reduced sizes of MOS field effect transistors, which affect electron and hole mobility, necessitating improvements in semiconductor device performance.
Innovation Solution
A method of manufacturing semiconductor devices involving the formation of active patterns, dummy gate patterns, gate spacers, channel recess regions, and channel patterns with selective epitaxial growth, where the channel pattern has a lattice constant different from the semiconductor substrate, and is covered by a gate dielectric layer and gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS field effect transistors are highly integrated with reduced sizes, then device density increases, but electron and hole mobility deteriorates
Solution Approach 1:
The patent applies local quality by forming a channel pattern with a different lattice constant (e.g., SiGe or III-V material) specifically in the channel region between source and drain, while the rest of the transistor structure uses standard silicon. This localized material substitution improves charge mobility in the critical channel region without affecting other device regions, thereby resolving the contradiction between high integration density and charge mobility.
2Ease of manufacture
If dummy gate pattern is formed before channel recess, then gate structure is established early, but channel pattern formation becomes complex
Solution Approach 1:
The patent uses preliminary action by forming the dummy gate pattern before creating the channel recess. The dummy gate serves as a placeholder that defines the gate region boundaries early in the process, enabling subsequent selective epitaxial growth of the channel pattern in the exposed regions. This preliminary gate formation simplifies the overall manufacturing sequence by establishing reference structures before complex channel patterning.
Solution Approach 2:
The dummy gate acts as an intermediary element that facilitates the formation process. It temporarily occupies the gate region, allowing selective etching and epitaxial growth to create the channel pattern with precise lateral confinement. After channel formation, the dummy gate is removed and replaced with the actual gate electrode, demonstrating how the intermediary structure enables complex channel patterning while maintaining manufacturing simplicity.
3Reliability
If channel pattern with different lattice constant is formed, then charge mobility improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service through selective epitaxial growth, where the channel pattern forms automatically only in regions where the semiconductor substrate is exposed after dummy gate removal. The epitaxial process inherently confines growth to the intended areas through selective area growth mechanisms, reducing the need for additional patterning steps and lowering manufacturing precision requirements despite the complexity of forming heteroepitaxial structures with different lattice constants.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical characteristics and mobility of charges in fin field effect transistors by forming a channel pattern with a distinct lattice constant, improving device performance and preventing damage during the dummy gate removal process.
Implementation Method 1
forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, the channel pattern having sidewalls and having a lattice constant different from that of the semiconductor substrate
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.