3D Semiconductor Device Channel Pillar Contact Optimization
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in enhancing operational reliability, particularly in the manufacturing process, which affects the integration density and performance of memory cells.
Innovation Solution
A manufacturing method for a three-dimensional semiconductor device involving the sequential stacking of semiconductor layers, formation of channel pillars, and a gate stack structure, with a third semiconductor layer filling annular grooves to enhance contact with channel pillars and improve erase current characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory strings are arranged to increase integration density, then device capacity increases, but manufacturing complexity and operational reliability deteriorate
Solution Approach 1:
The semiconductor device is divided into multiple semiconductor layers (first, second, and third semiconductor layers) stacked vertically, with memory strings segmented across these layers. This segmentation allows for better control of each layer's properties and reduces manufacturing complexity while maintaining high integration density.
Solution Approach 2:
The third semiconductor layer is positioned specifically between the first and second semiconductor layers and makes contact with channel pillars at localized positions. This local quality approach optimizes electrical characteristics and erase current distribution in critical areas without requiring uniform modification throughout the entire device structure.
2Ease of manufacture
If conventional manufacturing processes are used for three-dimensional devices, then device structure is formed, but operational reliability and erase current characteristics are insufficient
Solution Approach 1:
The third semiconductor layer is formed in advance between the first and second semiconductor layers before final device assembly. This preliminary action ensures proper positioning and contact with channel pillars, leading to improved erase current characteristics and operational reliability while maintaining manufacturing feasibility.
Solution Approach 2:
The invention transitions from a two-dimensional planar structure to a three-dimensional stacked structure by introducing the third semiconductor layer vertically between existing layers. This dimensional change enables better control of electrical characteristics and improves erase operation performance without significantly complicating the manufacturing process.
Data Source
AI summary
A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.