Semiconductor Channel Protrusion for Contact Overlay Margin

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Solution Overview

Problem

The manufacturing process of semiconductor devices with channel patterns faces challenges due to the small surface area of the channel pattern, which results in insufficient overlay margin for forming contact plugs, affecting the integration and performance of three-dimensional memory devices.

Innovation Solution

A semiconductor device with a stacked structure of alternately stacked conductive and interlayer insulating patterns, featuring a through-hole with a channel pattern protruding from it and a capping conductive pattern wider than the through-hole, enhancing the contact area and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the channel pattern is formed with a small surface area to achieve high integration density in three-dimensional memory devices, then the integration level is improved, but the overlay margin for forming contact plugs becomes insufficient

Engineering Contradiction:
Improveintegration densityVSAvoidoverlay margin
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The invention transitions from a two-dimensional contact area problem to a three-dimensional solution by forming a contact hole that extends vertically through multiple interlayer insulating patterns. The contact hole reaches down to the channel pattern, creating a vertical connection path that allows for adequate overlay margin in the horizontal plane while maintaining high integration density through the vertical stacking architecture

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The contact hole is formed nested within the stacked structure of alternately stacked conductive patterns and interlayer insulating patterns. The contact hole penetrates through multiple layers, with the channel pattern positioned at the bottom and conductive patterns arranged around it, creating a nested configuration that enables both high integration and sufficient contact area

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS10319737B2Semiconductor device and method of manufacturing the same
Publication Date: 2019.06.11 SK HYNIX INC
  • US10319737B2 patent drawing
  • US10319737B2 patent drawing
  • US10319737B2 patent drawing

AI summary

The semiconductor device includes a stacked structure having alternately stacked conductive patterns and interlayer insulating patterns, a through-hole passing through the stacked structure, a channel pattern formed in the through-hole and protruding from an inside of the through hole over the through-hole, and a capping conductive pattern formed to be in contact with the protruded channel pattern and have a width greater than the through-hole.