Semiconductor Channel Layout With Stepped Source/Drain Geometry
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Solution Overview
Problem
As semiconductor devices are scaled down, their operation characteristics deteriorate, necessitating improved methods for high-integration and enhanced performance.
Innovation Solution
A semiconductor device design featuring distinct active patterns with varying channel and source/drain widths and levels, along with a gate electrode configuration that optimizes the layout and material composition to enhance electrical characteristics and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If metal-oxide-semiconductor field effect transistors are scaled down to achieve higher integration, then device density increases, but operation characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating different channel width configurations for first and second active patterns. The first channel pattern has a width that differs from the second channel pattern, allowing each region to be optimized for specific electrical characteristics. This enables high integration density while maintaining reliable operation characteristics through localized structural variations.
Solution Approach 2:
The patent employs asymmetry by designing the first active pattern and second active pattern with different geometrical characteristics. The first channel pattern has a width that is intentionally made different from the second channel pattern, creating asymmetric structures that compensate for scaling effects and maintain electrical performance at high integration densities.
2Ease of manufacture
If source/drain patterns are formed at the same level as channel patterns, then manufacturing process is simplified, but overgrowth and undergrowth issues occur
Solution Approach 1:
The patent resolves the manufacturing precision issue by transitioning from a two-dimensional planar configuration to a three-dimensional vertical configuration. The source/drain patterns are formed at a different vertical level than the channel patterns, creating a stepped structure. This dimensional change allows for better control of pattern dimensions while maintaining manufacturing feasibility through selective epitaxial growth.
Data Source
AI summary
Provided is a semiconductor device including a first active pattern and a second active pattern on a substrate, a first source/drain pattern and a first channel pattern on the first active pattern, a second source/drain pattern and a second channel pattern on the second active pattern, and a gate electrode crossing each of the first channel pattern and the second channel pattern. Along a horizontal extension direction of the gate electrode, a first width of an upper surface of the first channel pattern is greater than a second width of an upper surface of the second channel pattern, and an upper surface of the first source/drain pattern is located at a vertically higher level than the upper surface of the first channel pattern.