Semiconductor Channel Stress via Dislocation Line Angles
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Solution Overview
Problem
Existing semiconductor devices face challenges in generating sufficient strain in the channel region to enhance carrier mobility, as prior methods introduce only small strains, which limits the performance improvement of transistors.
Innovation Solution
A semiconductor device and manufacturing method that utilize pre-amorphization implantation and annealing to create crystal lattice dislocation lines at specific angles, generating compressive or tensile stress in the channel region, combined with the use of a second semiconductor material like SiGe or Si:C to increase strain, while maintaining compatibility with existing integrated circuit processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional strain introduction methods are used, then the device structure remains simple, but the strain magnitude in the channel region is insufficient to significantly enhance carrier mobility
Solution Approach 1:
The patent introduces dislocation lines with specific orientations (angles) relative to the channel direction, transforming the strain introduction from a simple magnitude problem to a directional control problem. By controlling the angle of dislocation lines, the patent achieves both high strain magnitude and selective stress type (tensile or compressive) in the channel region.
Solution Approach 2:
The patent changes the orientation parameter (angle) of dislocation lines to control the type and magnitude of stress in the channel. By adjusting the angle parameter, the patent can switch between tensile and compressive stress states, and control the strain magnitude, thereby resolving the contradiction between simple structure and high strain magnitude.
2Reliability
If stress is applied to increase carrier mobility, then transistor performance improves, but the strain introduced by conventional methods is too small to achieve significant performance enhancement
Solution Approach 1:
The patent performs pre-amorphization implantation before forming the dislocation lines, preparing the semiconductor lattice in advance to facilitate the introduction of high-magnitude strain. This preliminary action enables the subsequent formation of dislocation lines to generate significant strain without compromising device reliability.
Solution Approach 2:
The patent uses a combination of dislocation lines with specific orientations and materials (such as SiGe or Si:C) to achieve high strain magnitude. The composite approach of combining structural features (dislocation lines) with material properties enables significant strain introduction that enhances carrier mobility and transistor performance.
3Reliability
If different stress types are needed for NMOS and PMOS devices, then carrier mobility for each device type can be optimized, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies different dislocation line orientations locally to different device regions: NMOS devices receive dislocation lines with angles greater than or equal to 90° to generate tensile stress, while PMOS devices receive dislocation lines with angles less than or equal to 90° to generate compressive stress. This local differentiation optimizes carrier mobility for each device type while maintaining a unified manufacturing approach.
Solution Approach 2:
The patent introduces asymmetric dislocation line orientations relative to the channel direction, with different angle requirements for NMOS and PMOS devices. This asymmetry in dislocation line configuration enables differentiated stress states (tensile for NMOS, compressive for PMOS) that optimize carrier mobility for each device type, while the asymmetric approach is integrated into a symmetric manufacturing process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively generates significant uniaxial tensile and compressive strains close to the channel, enhancing carrier mobility without altering the fundamental device structure, thus improving transistor performance and being highly compatible with existing integrated circuit processes.
Implementation Method 1
performing pre-amorphization implantation to the semiconductor substrate, which implants ion into the semiconductor substrate through the groove so as to generate an amorphized region in the semiconductor substrate
Implementation Method 2
annealing the semiconductor substrate, during which the amorphized region is subject to a solid phase epitaxial growth to generate a crystal lattice dislocation line under the gate structure
Data Source
AI summary
A semiconductor device and its manufacturing method are provided. The semiconductor device comprises: a semiconductor substrate of a first semiconductor material, a gate structure on the semiconductor substrate, a crystal lattice dislocation line in a channel under the gate structure for generating channel stress, wherein the crystal lattice dislocation line being at an angle to the channel.