3D Semiconductor Channel Trenches for Alignment and Cell Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing 3D semiconductor devices face challenges in increasing memory cell density and alignment issues during manufacturing, particularly in forming channel trenches and select gate cut structures, which can lead to increased costs and thermal stress.
Innovation Solution
The formation of channel trenches through both a stack structure and a select gate layer, with a layered structure including a blocking layer, charge trapping layer, and dielectric layer, allows for a floating gate configuration and reduces the need for additional etching processes, enhancing memory cell density and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If channel trenches are formed through both stack structure and select gate layer separately, then manufacturing precision can be maintained, but manufacturing complexity and costs increase due to additional etching processes
Solution Approach 1:
The patent combines the formation of channel trenches through the stack structure and select gate layer into a single etching process. The select gate layer is configured to be etched simultaneously with the stack structure, eliminating the need for separate etching steps and reducing manufacturing complexity while maintaining alignment precision through the integrated structure design.
Solution Approach 2:
The select gate layer serves multiple functions: it acts as both a gate structure for transistor control and as part of the channel trench formation process. By making the select gate layer etchable and integrating it into the channel trench formation, the patent achieves multi-functionality that reduces the number of process steps required.
2Manufacturing precision
If dummy channels are added to improve alignment, then manufacturing precision improves, but memory cell density decreases
Solution Approach 1:
The patent performs preliminary structuring of the select gate layer with cut structures that define precise alignment references before the etching process. These pre-formed cut structures serve as alignment guides that enable accurate channel trench formation without requiring dummy channels, thereby maintaining both precision and density.
Solution Approach 2:
Instead of using dummy channels as alignment references, the patent creates a different type of alignment reference through the select gate cut structures. These cut structures copy the alignment function traditionally performed by dummy channels but without the penalty of reducing memory cell density, as they are formed within the functional structure rather than as separate alignment features.
3Reliability
If select gate layer is made of different material than gate lines, then device functionality is improved, but manufacturing complexity increases due to additional material deposition steps
Solution Approach 1:
The patent segments the gate structure into different materials with distinct functions: the gate lines use one material (e.g., polysilicon) for transistor gating, while the select gate layer uses a different material (e.g., doped polysilicon or metal) for selectivity and etching compatibility. This segmentation allows each material to be optimized for its specific function while the selective etching capability enables separate processing.
Solution Approach 2:
Different regions of the gate structure have different material properties tailored to their specific functions. The select gate layer has different material composition compared to gate lines, providing local quality variations that enable selective etching and different electrical characteristics. This local differentiation is achieved through targeted material deposition and doping processes.
Data Source
AI summary
Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes a stack structure with at least one gate line, a select gate layer and at least one channel structure. The at least one gate line includes a first material. The select gate layer includes a second material different from the first material. The at least one channel structure extends through the stack structure and the select gate layer along a first axis. Each channel structure of the at least one channel structure includes a layered structure.