Semiconductor Channel Pattern With Well Contact Line
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in enhancing operational reliability due to limitations in the integration and arrangement of memory cell transistors and select transistors, which affect data storage and retrieval efficiency.
Innovation Solution
A semiconductor device design featuring a channel pattern with horizontal and vertical parts, a gate stack enclosing the vertical parts, a well structure with a specific conductivity type impurity, and a well contact line that couples the channel pattern with the well structure, along with a method of manufacturing that includes forming through holes and well contact lines to enhance electrical coupling and control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cell transistors and select transistors are stacked in three-dimensional arrangement to increase integration, then device integration is improved, but operational reliability deteriorates due to current flow control issues and leakage
Solution Approach 1:
The channel layer is segmented into multiple distinct channel patterns (first channel pattern, second channel pattern, etc.) with separate well contact structures for each. This segmentation allows independent control of current flow paths for different transistor groups, improving reliability while maintaining high integration through the 3D stacked arrangement.
Solution Approach 2:
Well contact lines and well contact structures serve as intermediary elements that mediate between the channel patterns and the well structure. These intermediaries provide controlled electrical coupling and current flow management, preventing direct uncontrolled current paths that would cause leakage while maintaining the compact 3D structure.
2Reliability
If well contact lines are formed to couple channel patterns with well structure, then current flow control is improved, but device complexity increases
Solution Approach 1:
Multiple well contact lines are merged and coupled to a shared well structure, reducing the overall number of discrete components needed. The well contact structures integrate multiple functions (electrical coupling, current control, structural support) into unified elements, managing complexity while maintaining effective current flow control across the 3D device.
3Reliability
If through holes are formed to create well contact lines, then electrical coupling is improved, but manufacturing precision requirements increase
Solution Approach 1:
Through holes are formed and well contact lines are established during the manufacturing process before final device operation. This preliminary action ensures proper electrical coupling and current flow paths are built-in during fabrication, reducing the need for post-manufacturing adjustments and managing precision requirements through controlled manufacturing steps rather than operational adjustments.
Data Source
AI summary
The semiconductor device includes: a first channel pattern including a first horizontal part, vertical parts extending from the first horizontal part, a connection part extending from the first horizontal part in a direction opposite to the vertical parts, and a second horizontal part extending from the connection part in a direction parallel to the first horizontal part; a first gate stack enclosing the vertical parts of the first channel pattern and disposed over the first horizontal part; a well structure disposed under the second horizontal part, and including a first conductivity type impurity; and a first well contact line directly contacting with the second horizontal part and the well structure to couple the second horizontal part of the first channel pattern with the well structure.