Semiconductor Charge-Dispersing Layout for Gate Arcing Protection

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Solution Overview

Problem

Existing semiconductor devices face challenges in reducing damage to peripheral circuit structures as they become smaller, particularly due to arcing issues during manufacturing processes.

Innovation Solution

Incorporating a semiconductor device design that includes a transistor with a gate insulating layer and gate electrode, a first diode in a substrate region, a second diode in an insulating layer, and interconnections connected to both diodes and the gate electrode, which disperses charges to prevent damage to the gate insulating layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the semiconductor device is scaled down to reduce area, then the area of the semiconductor memory device is reduced, but arcing damage to the gate insulating layer increases

Engineering Contradiction:
Improvearea of semiconductor memory deviceVSAvoidarcing damage to gate insulating layer
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

A charge dispersing structure (comprising diodes and interconnections) is introduced as an intermediary element between the peripheral circuit and the gate insulating layer. This structure captures and disperses charges that would otherwise accumulate and cause arcing damage, thereby protecting the gate insulating layer while allowing continued device scaling

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The charge dispersing structure extends the peripheral circuit into a third dimension by forming diodes and interconnections that penetrate through insulating layers. This vertical dimensionality allows charge dispersal pathways to be established without increasing the planar area of the device

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of stationary object

If the peripheral circuit structure is disposed under the memory cells to reduce area, then the area is reduced, but the complexity of preventing arcing damage increases

Engineering Contradiction:
Improvearea of semiconductor memory deviceVSAvoidcomplexity of preventing arcing damage
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The charge dispersing function is segmented into discrete diode structures (first diode in substrate, second diode in insulating layer) connected through interconnections. This segmentation allows the charge dispersal function to be integrated into the existing peripheral circuit layout without requiring a complete redesign, thus managing complexity while protecting against arcing

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design effectively reduces arcing-related damage to the gate insulating layer, enhancing the reliability and integrity of the semiconductor device as process scaling increases.

Implementation Method 1

interconnections connected to the first diode, the second diode, and the gate electrode, respectively... which disperses charges to prevent damage to the gate insulating layer

Methodology Applied
Scientific EffectCharge dispersal: Conduction (electrical)

Data Source

PatentUS20250294892A1Semiconductor device and method of manufacturing the same
Publication Date: 2025.09.18 SK HYNIX INC
  • US20250294892A1 patent drawing
  • US20250294892A1 patent drawing
  • US20250294892A1 patent drawing

AI summary

Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a substrate including a first region and a second region, a transistor including a gate insulating layer and a gate electrode that are stacked over the first region of the substrate, a first diode, at least a portion of the first diode being formed in the second region of the substrate, an insulating layer disposed on the substrate, a second diode disposed in the insulating layer to be spaced apart from the substrate, and interconnections connected to the first diode, the second diode, and the gate electrode, respectively.