Semiconductor Charge Trap Site Ferroelectric Dielectric Structure
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Solution Overview
Problem
As semiconductor chip feature sizes decrease, maintaining the required capacitance in dielectric layers of capacitors and transistors while reducing leakage current and increasing breakdown voltage remains a challenge.
Innovation Solution
Incorporating a ferroelectric layer and a dielectric layer with charge trap sites in series, where the dielectric layer has a non-ferroelectric property and the ferroelectric layer exhibits negative capacitance, to enhance capacitance and reduce leakage current, and using barrier insulation layers to stabilize the material properties and prevent electron movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If high dielectric material is utilized in the dielectric layer, then capacitance is improved, but leakage current increases and breakdown voltage decreases
Solution Approach 1:
The dielectric layer is segmented into multiple sub-dielectric layers (first sub-dielectric layer, second sub-dielectric layer) with different materials and functions. The first sub-dielectric layer provides high capacitance, while the second sub-dielectric layer reduces leakage current and increases breakdown voltage, resolving the contradiction between capacitance and reliability
Solution Approach 2:
The patent uses composite material structure by combining different dielectric materials (e.g., hafnium oxide, silicon oxide, silicon nitride) in a layered configuration. Each material is selected for its specific properties, creating a composite dielectric system that achieves both high capacitance and high reliability
2Area of moving object
If feature size of semiconductor chip decreases, then device density is improved, but maintaining required capacitance becomes difficult
Solution Approach 1:
The patent changes the dielectric constant parameter by introducing high-k dielectric materials (hafnium oxide with high dielectric constant) into the dielectric layer structure, enabling sufficient capacitance to be achieved even with reduced feature sizes and smaller capacitor areas
Solution Approach 2:
Instead of increasing capacitance by enlarging the planar area of the capacitor, the patent transitions to the vertical dimension by creating multiple stacked sub-dielectric layers, effectively increasing capacitance through the third dimension while maintaining small feature sizes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases the overall capacitance of the semiconductor device, improves reliability by preventing electron pinning in the ferroelectric layer, and enhances endurance by stabilizing the ferroelectric and dielectric properties, while maintaining low leakage current and high breakdown voltage.
Implementation Method 1
the ferroelectric layer exhibits negative capacitance
Implementation Method 2
charge trap sites disposed in an inner region of the dielectric layer
Data Source
AI summary
A semiconductor device includes a first electrode, a ferroelectric layer disposed on the first electrode, a dielectric layer disposed on the ferroelectric layer, charge trap sites disposed in an inner region of the dielectric layer, and a second electrode disposed on the dielectric layer. The dielectric layer may have a non-ferroelectric property. The dielectric layer and the ferroelectric layer are disposed between the first electrode and the second electrode and connected in series to each other. The semiconductor device may include charge trap sites distributed in an inner region of the dielectric layer having a non-ferroelectric property.