Semiconductor Check Pattern Layout to Prevent Dicing Chipping
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Solution Overview
Problem
The formation of a check pattern for inspection during semiconductor element manufacturing can lead to chipping and a reduction in the number of obtained semiconductor elements due to the inclusion of a drop-in region, which is not part of the final product.
Innovation Solution
A semiconductor element design that includes a conductive layer with a check pattern not electrically connected to the circuit, featuring a superimposition portion on the check pattern visible in the thickness direction, and a manufacturing method involving the formation of vias and a conductive layer with a seed layer, allowing for visual inspection of the check pattern's positional relation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a check pattern is formed in a dicing region for inspection, then inspection capability is improved, but chipping occurs during dicing and the number of semiconductor elements obtained decreases
Solution Approach 1:
The check pattern is moved from the planar surface (2D) to the vertical cross-section (3D) by forming it within via holes that penetrate the passivation film. This dimensional transition allows the check pattern to be positioned in the thickness direction rather than occupying additional lateral space, thereby maintaining productivity while enabling inspection capability.
2Measurement precision
If a check pattern including hard metal is formed, then inspection capability is improved, but chipping occurs during dicing
Solution Approach 1:
The check pattern is relocated to the vertical dimension within via holes, positioning it away from the dicing cut path. This eliminates the mechanical interaction between the hard metal check pattern and the dicing blade, preventing chipping while preserving the inspection function through visual or optical examination of the via region.
3Measurement precision
If a drop-in region is provided within one shot of photomask, then check pattern can be disposed, but the number of semiconductor elements obtained decreases
Solution Approach 1:
The check pattern is formed within via holes that extend through the passivation film in the thickness direction, utilizing the vertical dimension rather than consuming lateral photomask area. This eliminates the need for a drop-in region, allowing all semiconductor elements within one photomask shot to be productive while maintaining inspection capability through the via-based check pattern.
Data Source
AI summary
Provided is a semiconductor element including a semiconductor substrate; a semiconductor layer laminated to the semiconductor substrate, and having a circuit formed within the semiconductor layer; a conductive layer disposed on an opposite side of the semiconductor layer from the semiconductor substrate and including a part electrically connected to the circuit; and a conductive portion disposed between the semiconductor layer and the conductive layer, and electrically connected to the conductive layer. The conductive layer includes a check pattern not electrically connected to the circuit, and the conductive portion includes a superimposition portion superimposed on the check pattern as viewed in a thickness direction of the semiconductor substrate.