Semiconductor Chip Integration Using Low Young's Modulus Adhesive
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Solution Overview
Problem
Current semiconductor integration methods, such as System-On-Chip (SOC) and System-In-Package (SIP), face challenges in achieving high integration, thin packaging, and low development costs due to limitations in device types, complexity, and thickness of MEMS devices, particularly when integrating MEMS devices with different materials and shapes.
Innovation Solution
A semiconductor apparatus and manufacturing method involving chips with adhesive layers of lower Young's modulus than the chip materials, allowing for bonding and integration of MEMS and semiconductor devices, with the use of temporary adhesive layers for chip transfer and polishing to achieve uniform heights and minimize passivation film thickness, thereby facilitating thinner and more complex chip structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If System-On-Chip (SOC) method is used to integrate all devices on one chip, then high device integration and minute global wires can be achieved, but the types of devices that can be integrated are limited due to differences in lattice constant and thermal expansion rate between different materials
Solution Approach 1:
The patent divides the integration system into multiple independent chips that can be formed separately using different semiconductor materials and processes. Each chip maintains its material properties while being integrated into a single package, allowing diverse device types (silicon, GaAs, etc.) to coexist without lattice mismatch or thermal expansion conflicts.
Solution Approach 2:
The patent introduces an interposer substrate as an intermediary component between different material chips. This interposer serves as a mechanical and electrical bridge that accommodates different thermal expansion rates and lattice constants, enabling heterogeneous device integration while maintaining structural integrity and electrical connectivity.
2Adaptability or versatility
If System-In-Package (SIP) method is used with independent chip formation and mounting on interposer, then various device types can be integrated with lower development costs, but higher density of chips and thinner packages are difficult to achieve due to bonding wires or bumps
Solution Approach 1:
The patent extracts the connection function from traditional bonding wires and bumps by implementing direct chip-to-chip bonding interfaces. This eliminates the intermediate connection elements that consume space and limit density, allowing chips to be positioned closer together while maintaining electrical connectivity through direct bonding.
Solution Approach 2:
The patent transitions from planar chip arrangement to three-dimensional stacking configurations. By bonding chips vertically in multiple layers rather than only horizontally, the system achieves higher integration density within a compact package volume, reducing the overall package thickness despite multiple device types.
3Ease of manufacture
If chips with vertical section are embedded in concave portions, then embedding is difficult, but if chips are made with tapered section, then embedding is easier
Solution Approach 1:
The patent applies different geometric characteristics to different regions of the chip structure. The chip edges are designed with tapered profiles to facilitate embedding and alignment, while the central active region maintains its standard planar geometry to preserve device functionality. This localized geometric modification enables easy embedding without compromising the vertical section requirements of the active devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables highly integrated and thinned semiconductor devices with reduced development costs and shorter development periods, overcoming limitations of existing methods by allowing for diverse device integration and minimizing thermal stress-induced warping and cracking.
Implementation Method 1
minimize thermal stress-induced warping and cracking
Implementation Method 2
an adhesive layer bonding a side face of the first chip to a side face of the second chip
Data Source
AI summary
It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young's modulus than the material of the first and second chips.