Semiconductor Device Chip Alignment for Gate Response Speed
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Solution Overview
Problem
Semiconductor devices face challenges in downsizing while maintaining high-current capability and preventing a decrease in gate response speed, as existing arrangements of circuit patterns, semiconductor chips, and wires are not optimal for both high area efficiency and fast gate response.
Innovation Solution
A semiconductor device design that aligns semiconductor chips and control electrodes on circuit patterns with strategically placed control wires to prevent a decrease in gate response speed and optimize chip mounting area, allowing for increased output current while minimizing heat generation and temperature increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a plurality of semiconductor chips are disposed on a circuit pattern with high area efficiency for downsizing and high-current capability, then the area efficiency is improved, but the gate response speed decreases
Solution Approach 1:
The patent changes the arrangement dimension from scattered placement to linear alignment along a specific direction. Multiple semiconductor chips are disposed in a line with their side portions and control electrodes aligned, allowing control wires to connect sequentially. This dimensional organization reduces wire length and improves gate response speed while maintaining high area efficiency.
Solution Approach 2:
The patent merges the control electrode connections by using a single control wire that sequentially connects multiple control electrodes along the alignment direction. This consolidation reduces the number of separate connections needed and optimizes the control signal transmission path, improving gate response speed without sacrificing chip mounting density.
2Area of stationary object
If circuit patterns and wires are arranged to maximize chip mounting area, then area efficiency is improved, but the arrangement becomes non-optimal for gate response speed
Solution Approach 1:
The patent applies local quality optimization by specifically aligning the control electrodes and arranging control wires along the alignment direction, while other parts of the circuit pattern can be optimized independently. This localized structural optimization ensures fast gate response in the control path without compromising overall area efficiency.
3Area of stationary object
If semiconductor chips are densely arranged for downsizing, then device size is reduced, but heat dissipation becomes more challenging
Solution Approach 1:
The patent segments the heat dissipation function by providing individual heat dissipation plates for each semiconductor chip. Even though chips are densely arranged, each chip has its own dedicated heat dissipation path, preventing heat accumulation and maintaining effective thermal management in the compact device structure.
Data Source
AI summary
A semiconductor device, having a first semiconductor chip including a first side portion at a front surface thereof and a first control electrode formed in the first side portion, a second semiconductor chip including a second side portion at a front surface thereof and a second control electrode formed in the second side portion, a first circuit pattern, on which the first semiconductor chip and the second semiconductor chip are disposed, a second circuit pattern, and a first control wire electrically connecting the first control electrode, the second control electrode, and the second circuit pattern. The first side portion and the second side portion are aligned. The first control electrode and the second control electrode are aligned. The second circuit pattern are aligned with the first control electrode and the second control electrode.