Semiconductor Chip Arrangement With Asynchronous Data Channels
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Solution Overview
Problem
Conventional semiconductor chip arrangements require a large number of lines and connections for transmitting load control data, pilot data, and diagnostic data, leading to complexity and limitations in data transmission rates, especially with long line lengths.
Innovation Solution
The arrangement separates diagnostic data transmission via a first channel and load control and pilot data transmission via a second channel, allowing for asynchronous diagnostic data transmission without a dedicated clock line, reducing the number of lines needed and enabling high data transmission rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bidirectional data transmission is implemented on a single transmission channel, then the number of lines is reduced, but data transmission reliability deteriorates due to synchronization issues and limited data rates
Solution Approach 1:
The transmission channel is segmented into two separate unidirectional channels: one for downward transmission (microcontroller to power chip) and one for upward transmission (power chip to microcontroller). This segmentation eliminates synchronization conflicts and allows each channel to operate independently at optimized data rates, resolving the contradiction between line reduction and transmission reliability.
Solution Approach 2:
A transmission channel separation mechanism acts as an intermediary, directing different data types through dedicated paths. Downward data (load control data, pilot data) travels through one channel while upward data (diagnostic data, status information) travels through another, eliminating bidirectional conflicts without requiring excessive wiring.
2Device complexity
If synchronous bidirectional transmission is used, then data transmission is organized, but the data transmission rate is limited by signal propagation delays
Solution Approach 1:
Instead of using synchronous bidirectional transmission where both directions must coordinate timing, the invention inverts the approach by using two independent unidirectional channels. Each channel operates asynchronously without needing to wait for acknowledgment or coordinate with the other direction, eliminating propagation delay limitations while maintaining organized data flow.
Solution Approach 2:
The transmission system uses periodic sampling and interrupt-driven communication where data is transmitted in discrete packets rather than continuous synchronous streams. This allows the system to maintain organized transmission while achieving higher effective data rates by utilizing idle periods and avoiding continuous synchronization overhead.
3Reliability
If dedicated lines are provided for each load control signal, then transmission reliability is improved, but the number of lines and connections increases significantly
Solution Approach 1:
Multiple load control signals that were previously transmitted on separate dedicated lines are merged into a single serial transmission channel. The microcontroller transmits load control data sequentially through one channel, and the power chip reconstructs the original signals internally, achieving the same control functionality with far fewer physical connections while maintaining transmission reliability through error checking and acknowledgment protocols.
Solution Approach 2:
The single transmission channel serves multiple functions: it carries load control data, pilot data for power chip configuration, and handles acknowledgment signals. This multi-functional channel replaces numerous dedicated lines, reducing connection complexity while maintaining reliable communication through context-dependent data interpretation and protocol-based signal differentiation.
Data Source
AI summary
An arrangement including a first semiconductor chip and a second semiconductor chip connected thereto, where the second semiconductor chip is additionally connected to electrical loads and drives these electrical loads on the basis of a timing which is prescribed to it by load control data, and where the first semiconductor chip transmits to the second semiconductor chip the aforementioned load control data and pilot data which control the second semiconductor chip, and where the second semiconductor chip transmits to the first semiconductor chip diagnostic data which represent states prevailing in the second semiconductor chip or events which occur. The diagnostic data are transmitted via a first transmission channel and the load control data and the pilot data are transmitted via a second transmission channel.


