Semiconductor Device Chip-on-Chip Parallelism
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Solution Overview
Problem
In semiconductor manufacturing, the chip-on-chip (COC) structure faces challenges with maintaining parallelism and reducing stress-induced malfunctions due to size differences between upper and lower chips, leading to non-uniform transistor operation and increased manufacturing costs.
Innovation Solution
A semiconductor device design where a smaller first semiconductor chip is extended with an outward extension, allowing a second semiconductor chip to be bonded on top, ensuring parallelism through strategically placed bumps and external terminals, and reducing stress by distributing bumps across the chip surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the lower chip has a smaller area in the COC structure, then the mounting area is reduced, but a region enough for wire bonding cannot be formed
Solution Approach 1:
The invention transitions from planar wire bonding to three-dimensional bump bonding, allowing connections to be formed in the vertical dimension rather than requiring extensive lateral space. This enables the lower chip to have a smaller area while still achieving all necessary electrical connections through bumps formed on the chip surface.
2Device complexity
If the bumps are placed so as to be concentrated at the center of the chip, then the bonding process is simplified, but the upper chip becomes unstable and parallelism cannot be maintained
Solution Approach 1:
The invention employs asymmetric bump placement where additional bumps are positioned at the outer circumferential regions of the chip, creating an asymmetric distribution pattern. This asymmetric arrangement provides enhanced mechanical support and stability to the upper chip while maintaining the simplified bonding process through systematic placement rules.
Data Source
AI summary
A semiconductor device includes an extended semiconductor chip including a first semiconductor chip and an extension outwardly extending from a side surface of the first semiconductor chip; and a second semiconductor chip connected to the extended semiconductor chip through a plurality of bumps and electrically connected to the first semiconductor chip. The first semiconductor chip is smaller than the second semiconductor chip. At least one external terminal is provided on the extension.