Semiconductor Chip Bonding with Stress-Relief Junction
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Solution Overview
Problem
Semiconductor devices using soldering materials for bonding face issues such as stress-induced damage due to heat shrinkage differences and misalignment during the bonding process, particularly when using soldering materials like solder for bonding semiconductor chips to islands or lead frames.
Innovation Solution
A semiconductor device configuration with a junction plane smaller than the semiconductor chip's back surface, using a soldering material with varying grain sizes and melting points, and extending portions to facilitate precise alignment and bonding, preventing stress and misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soldering material is used as bonding material to bond semiconductor chip to island, then electrical connection is achieved, but stress-induced damage occurs due to heat shrinkage difference
Solution Approach 1:
The bonding structure is segmented into multiple functional layers: soldering material layer for electrical connection, intermediate layer for stress absorption, and insulating layer for electrical isolation. This segmentation allows each layer to perform its specific function while mitigating the harmful effects of thermal stress on the semiconductor chip.
Solution Approach 2:
An intermediate layer is introduced between the soldering material and the semiconductor chip to act as a stress-absorbing intermediary. This intermediate layer absorbs the thermal expansion and contraction stresses generated during temperature changes, preventing direct transmission of stress to the chip and avoiding crack formation.
2Strength
If reflow soldering is performed to bond semiconductor chip, then strong bonding is achieved, but misalignment occurs during cooling process
Solution Approach 1:
Alignment marks are pre-formed on both the semiconductor chip and the island before the bonding process. These alignment marks enable precise positioning and alignment of the chip relative to the island during the bonding process, ensuring that the chip remains correctly positioned even during the cooling phase when stress differential may cause shifting.
Solution Approach 2:
The bonding process utilizes controlled temperature parameters and cooling rates to minimize thermal stress-induced misalignment. By optimizing the heating and cooling parameters, the patent achieves strong bonding while reducing the magnitude of stress differential that causes misalignment during cooling.
3Stability of the object's composition
If island area is made larger to accommodate bonding, then bonding stability is improved, but stress concentration increases at peripheral portions
Solution Approach 1:
The island structure employs local quality differentiation with a larger overall area for stability, but with strategically positioned stress-relief features such as notches or reduced-density regions at peripheral portions. This allows the island to maintain bonding stability while reducing stress concentration at critical peripheral areas where cracks are most likely to form.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents stress-induced damage and improves alignment precision, enhancing the reliability and productivity of semiconductor device manufacturing by ensuring stable bonding and accurate positioning of semiconductor chips.
Implementation Method 1
the elastic recovery of the bonding material 107 prevents application of stress to the peripheral portion on the back surface side of the semiconductor chip 101
Implementation Method 2
when the temperature of the semiconductor device changes rapidly or drops after the bonding under high temperatures
Data Source
AI summary
The semiconductor device can prevent damages on a semiconductor chip even when a soldering material is used for bonding the back surface of the semiconductor chip to the junction plane of a chip junction portion such as an island or a die pad. This semiconductor device includes a semiconductor chip and a chip junction portion having a junction plane that is bonded to the back surface of the semiconductor chip with a soldering material. The junction plane is smaller in size than the back surface of the semiconductor chip. This semiconductor device may further include a plurality of extending portions which extend respectively from the periphery of the junction plane to directions parallel with the junction plane.