Semiconductor Chip Reference Clock Relay Mechanism

Solution Overview

Problem

Conventional semiconductor chip designs require multiple package pins and reference clock wirings to supply a reference clock to multiple SerDes hard macros, which increases board complexity and reduces routing performance.

Innovation Solution

A semiconductor chip configuration where a reference clock is supplied to one hard macro through a clock pad and relayed to other hard macros, reducing the number of necessary package pins and reference clock wirings on the board by using relay interconnections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple package pins and reference clock wirings are used to supply reference clock to multiple SerDes hard macros, then each hard macro can independently receive the reference clock, but the board complexity increases and routing performance decreases

Engineering Contradiction:

Improvereference clock supply reliabilityVSAvoidboard complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple reference clock inputs into a single shared input buffer. Instead of providing separate reference clock pins and wirings to each SerDes hard macro, the invention combines all reference clock inputs into one common buffer that serves multiple macros through internal relaying, thereby reducing board complexity while maintaining reliable clock supply to all macros

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent implements multi-functionality by making a single reference clock input buffer serve multiple SerDes hard macros. The shared input buffer acts as a universal clock source that can supply reference clocks to any number of hard macros on the chip, eliminating the need for dedicated reference clock paths for each macro

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple package pins and reference clock wirings are used to supply reference clock to multiple SerDes hard macros, then each hard macro can independently receive the reference clock, but the routing performance decreases

Engineering Contradiction:

Improvereference clock supply reliabilityVSAvoidrouting performance

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent merges multiple reference clock inputs into a single shared input buffer. Instead of providing separate reference clock pins and wirings to each SerDes hard macro, the invention combines all reference clock inputs into one common buffer that serves multiple macros through internal relaying, thereby reducing board complexity while maintaining reliable clock supply to all macros

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an intermediary relaying mechanism within the chip. The shared input buffer acts as an intermediary that receives the reference clock once and then distributes it to multiple hard macros through internal relaying paths, eliminating the need for multiple external wirings and improving routing efficiency

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7603579B2Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another

Publication Date: 2009.10.13 RENESAS ELECTRONICS CORP

AI summary

A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the plurality of hard macros. The reference clock supplied to the one hard macro is relayed to other hard macros of the plurality of hard macros in order.