Semiconductor Chip COC Structure Single Metal Conductor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor chip packaging technologies face challenges in achieving high density, small size, and high-speed operation due to high impedance and voltage drop issues in wire bonding, and impedance degradation in resin-embedded configurations.
Innovation Solution
A COC structure using a single metal conductor to connect semiconductor chips to external terminals, reducing impedance and signal attenuation, and eliminating wire bonding to simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect semiconductor chip terminals to external electrodes, then the connection is established, but the package size increases and impedance becomes high
Solution Approach 1:
The patent extracts and eliminates the wire bonding process from the semiconductor package structure. Instead of using separate bonding wires to connect chip terminals to external electrodes, the invention integrates the connection function directly into the chip structure through chip expansion portions that provide direct electrical contact points, thereby removing the need for additional bonding wires and reducing package area.
Solution Approach 2:
The patent merges the chip terminal function with the external electrode connection function by providing chip expansion portions that directly expose terminal contact points on the chip surface. This integration eliminates the need for separate wire bonding components, combining multiple functions into a single structural element that reduces overall package size.
2Reliability
If wire bonding is used to connect semiconductor chip terminals to external electrodes, then the connection is established, but the impedance becomes high and signal transmission speed decreases
Solution Approach 1:
The patent removes the wire bonding intermediate connection layer that causes high impedance and signal degradation. By directly exposing terminal contact points through chip expansion portions, the invention creates a low-impedance direct connection path that enables high-speed signal transmission without the interference of bonding wires.
3Reliability
If wire bonding is used for power supply connection, then the connection is established, but voltage drop occurs in the power source
Solution Approach 1:
The patent eliminates wire bonding from the power supply connection path, removing the source of voltage drop and energy loss. By providing direct terminal contact through chip expansion portions, the invention creates a low-resistance power delivery path that maintains stable voltage levels and reduces energy waste.
4Reliability
If wire bonding process is used, then the connection is established, but the manufacturing process becomes complex
Solution Approach 1:
The patent removes the wire bonding manufacturing process entirely from the semiconductor fabrication sequence. The chip expansion portions with exposed terminals are formed through standard chip fabrication processes, eliminating the need for separate wire bonding equipment, process parameters, and quality control steps, thereby simplifying manufacturing.
5Device complexity
If terminals are connected to wiring layer through bump terminals in resin-embedded configuration, then wire bonding is eliminated, but impedance in joint between terminal and wiring layer degrades frequency band characteristics
Solution Approach 1:
The patent extracts and eliminates the problematic intermediate bump terminal and wiring layer joint structure from the resin-embedded configuration. By providing direct terminal contact points through chip expansion portions, the invention creates a direct connection path that avoids the impedance issues associated with multiple intermediate connection layers and joint interfaces.
Data Source
AI summary
In a semiconductor device, a first semiconductor chip having a main surface provided with a first terminal group including terminals, and a rear face mounted on a surface of a support. A second semiconductor chip has a main surface provided with a second terminal group including terminals, the main surface of the second semiconductor chip facing the main surface of the first semiconductor chip, and each of the terminals in the second terminal group being connected to a corresponding one of the terminals in the first terminal group of the first semiconductor chip. The first semiconductor chip is connected to an external terminal of the semiconductor device via a conductor containing a single metal.