Semiconductor Chip Contact Stack Topology for Stress Reduction

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Solution Overview

Problem

Existing semiconductor chips with full multilayer contact stacks exhibit uneven topologies and increased mechanical stress at edge portions due to the height of the contact stacks over passivation layers, which can lead to performance issues during thermocycles and soldering processes.

Innovation Solution

A semiconductor chip design where at least one layer of a multilayer contact stack is removed from the passivation layer and boundary regions, leaving a reduced number of layers over the passivation layer, with a remaining layer acting as an etch stop or non-wettable barrier to prevent solder overflow and shorts, and a protection layer is formed to safeguard against soldering residues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a full multilayer contact stack is formed over the passivation layer and contact areas, then electrical connectivity and solderability are improved, but the chip topology becomes uneven and mechanical stress increases at edge portions

Engineering Contradiction:

Improveelectrical connectivityVSAvoidmechanical stress

Core Design Contradiction:

ReliabilityVSStress or pressure

Solution Approach 1:

The patent applies local quality by differentiating the contact stack structure in different regions: the first contact area receives the complete multilayer contact stack for optimal electrical connectivity, while the passivation layer region receives only a reduced number of layers. This spatial differentiation resolves the contradiction by providing full connectivity where needed while reducing mechanical stress in regions where the full stack would create uneven topology and stress concentration at edge portions.

Inventive Principle:

Principle #3Local quality

2Reliability

If a full multilayer contact stack is formed over the passivation layer, then electrical connectivity is improved, but the chip topology becomes uneven leading to performance issues during thermocycles

Engineering Contradiction:

Improveelectrical connectivityVSAvoidtopology uniformity

Core Design Contradiction:

ReliabilityVSStability of the object's composition

Solution Approach 1:

The patent implements local quality by creating region-specific contact stack configurations: complete multilayer stacks over contact areas for electrical connectivity, and reduced-layer structures over the passivation layer for topology uniformity. This resolves the contradiction between maintaining connectivity and ensuring topology stability during thermocycles by allowing each region to have the appropriate structure for its function.

Inventive Principle:

Principle #3Local quality

3Area of stationary object

If the contact stack extends over the passivation layer, then contact area coverage is improved, but solder overflow and shorts between contact areas may occur

Engineering Contradiction:

Improvecontact area coverageVSAvoidsolder overflow

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by creating a spatially varying contact stack structure where the first contact area has the complete multilayer stack for adequate coverage, while the passivation layer region has reduced layers that act as a barrier. This resolves the contradiction by providing sufficient contact area coverage where needed while preventing solder overflow in regions where it would cause harmful effects.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The reduced-layer structure over the passivation layer serves as an intermediary element between the contact areas. It provides a transitional structure that maintains electrical connectivity while acting as a physical barrier to prevent solder overflow and shorts, thus resolving the contradiction between coverage and harmful effects.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Stress or pressure

If at least one layer is removed from the passivation layer region, then mechanical stress is reduced and topology is flattened, but electrical connectivity in that region must be maintained

Engineering Contradiction:

Improvemechanical stressVSAvoidelectrical connectivity

Core Design Contradiction:

Stress or pressureVSReliability

Solution Approach 1:

The patent resolves this contradiction by applying local quality: the first contact area maintains the complete multilayer contact stack for optimal electrical connectivity, while the passivation layer region has reduced layers that lower mechanical stress. The boundary region serves as a transition zone, ensuring that electrical connectivity is maintained in the contact area while stress is reduced in the passivation region.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS11164830B2Semiconductor chip and method of processing a semiconductor chip

Publication Date: 2021.11.02 INFINEON TECHNOLOGIES AG

AI summary

Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.