Semiconductor Chip Independent Core Memory Power Control
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Solution Overview
Problem
Existing semiconductor chip designs face challenges in minimizing power consumption when processor elements (PEs) lend or borrow memory, as both PEs remain in an on state even if one core is not used, leading to unnecessary power waste.
Innovation Solution
The semiconductor chip incorporates a control unit that independently manages the power and clock supply to each processing device, allowing for the power and clock to be turned off for unused cores and memories, with a power gate or clock gate control unit to manage power and clock distribution based on control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both PEs are maintained in on state when memory lending/borrowing occurs, then communication between PEs can be established, but power consumption increases unnecessarily
Solution Approach 1:
The patent divides the PE into separate controllable components: the core (arithmetic unit) and the individual memory (LS), each with independent power control. This segmentation allows the memory to remain operational while the core is powered down, enabling memory lending/borrowing functionality without requiring both PEs to be fully operational, thus reducing unnecessary power consumption while maintaining communication capability.
Solution Approach 2:
The patent implements dynamic power control where the power supply state of each PE component can be changed based on operational needs. The control unit dynamically adjusts power distribution to turn off the core when not needed while keeping the memory active for lending/borrowing operations, transforming the static on/off state into a dynamic,需求-based power management system.
2Adaptability or versatility
If the core of an unused PE is supplied with power, then the PE can respond to communication requests, but power is wasted when the core is not actually used
Solution Approach 1:
By segmenting the PE into core and memory components with independent power control, the system can maintain memory functionality (needed for lending/borrowing) while powering down the core when not required for communication, eliminating power waste while preserving adaptability.
Solution Approach 2:
The patent applies local quality control by providing different power states to different components of the PE based on their specific operational needs. The memory receives power when needed for data storage and communication, while the core receives power only when actually required for arithmetic operations, optimizing energy efficiency.
Data Source
AI summary
Disclosed herein is a semiconductor chip including: a plurality of processing devices that can communicate with each other; wherein each of the processing devices includes an arithmetic unit, an individual memory connected to the arithmetic unit on a one-to-one basis, and a control unit configured to independently control turning on and off of operation of the arithmetic unit and the individual memory.