Semiconductor Chip Corner Openings for Adhesion Strength
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Solution Overview
Problem
In semiconductor chip packaging, stress due to thermal expansion coefficient differences between materials leads to uneven adhesion strength, causing delamination and reliability issues in packaged structures.
Innovation Solution
A method involving the formation of semiconductor structures with a substrate, connection layer, conductive bumps, and passivation layers, including third openings in corner regions to enhance adhesion strength by increasing roughness and distributing stress, thereby improving the reliability and performance of packaged structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging methods are used without additional openings in corner regions, then the manufacturing process is simple, but the adhesion strength is uneven and delamination occurs due to thermal expansion stress
Solution Approach 1:
The patent applies local quality by adding third openings specifically in the corner regions of the semiconductor chip, rather than uniformly across the entire chip. The corner regions are identified as high-stress areas due to thermal expansion coefficient differences, and the additional openings in these specific locations provide localized stress relief and improved adhesion where it is most needed, without unnecessarily complicating the entire structure.
Solution Approach 2:
The patent segments the passivation layer by creating multiple openings (first openings in conductive bump regions, second openings in non-conductive bump regions, and third openings in corner regions). This segmentation allows different regions of the chip to have different structural characteristics optimized for their specific functional requirements, improving overall adhesion strength while managing thermal stress distribution.
2Strength
If the passivation layer is made smooth and continuous, then the manufacturing process is simple, but the adhesion strength between chip and printed circuit board is insufficient under thermal stress
Solution Approach 1:
The patent introduces porosity into the passivation layer by forming multiple openings (first, second, and third openings) that penetrate through the passivation layer to expose the underlying connection layer or substrate. These openings create a porous structure that increases the surface area for adhesive bonding and allows the adhesive to mechanically interlock with the structure, significantly improving adhesion strength despite the increased fabrication complexity.
Data Source
AI summary
A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.