Semiconductor Chip Double Bump Structure for Probe Test Access
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Solution Overview
Problem
Existing semiconductor chip testing methods using wires or direct bumps face challenges in efficiently performing electrical tests and assembly, particularly when integrating with electronic substrates like smart cards, due to limitations in connectivity and test accessibility.
Innovation Solution
A double bump structure on semiconductor chips, comprising a first bump and a second bump, where the second bump is positioned on the side of the first bump, creating a test area accessible by a probe tip, allows for effective electrical testing and assembly via an anisotropic conductive film (ACF) connection to electronic substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single bump structure is used for connecting semiconductor chip to electronic substrate, then the assembly process is simplified, but electrical testing becomes difficult or impossible
Solution Approach 1:
The connection structure is segmented into two distinct bumps: a first bump for electrical testing and a second bump for final assembly. This segmentation allows the testing function and assembly function to be performed by separate structures, resolving the contradiction between test accessibility and assembly simplicity.
Solution Approach 2:
The first bump acts as an intermediary element that enables electrical testing before the final assembly. It serves as a temporary test interface that can be accessed by probe tips, allowing quality verification without interfering with the final assembly process using the second bump.
2Difficulty of detecting and measuring
If a probe tip needs to access the bump for testing, then electrical testing can be performed, but the bump structure becomes more complex
Solution Approach 1:
By dividing the connection structure into two separate bumps rather than modifying a single bump, the complexity is localized to specific elements rather than the entire structure. The first bump is designed specifically for testing with probe access, while the second bump maintains a simple form for assembly.
Solution Approach 2:
The first bump is specifically designed with local characteristics suitable for testing (exposed surface for probe contact), while the second bump has characteristics optimized for assembly. This local differentiation allows each element to be optimized for its specific function without unnecessarily complicating the other.
3Reliability
If the bump is completely covered for assembly protection, then reliability is improved, but test accessibility is reduced
Solution Approach 1:
The connection function is divided between two bumps: the first bump remains accessible for testing while the second bump provides the protective covering for assembly. This segmentation allows both test accessibility and connection reliability to be achieved simultaneously through separate structures.
Solution Approach 2:
Electrical testing using the first bump is performed before the final assembly process. This preliminary action allows verification of electrical functionality while the bump structure is still accessible, before any protective covering or final positioning is applied.
Data Source
AI summary
Provided is a semiconductor chip having a double bump structure. The semiconductor chip may include a semiconductor substrate, a circuit region on a surface of the semiconductor substrate, a pad on the semiconductor substrate and connected to the circuit region, a first bump on the pad, and a second bump on the first bump. The second bump may be arranged at one side of an upper surface of the first bump and the upper surface of the first bump may include a test area configured to interface with a probe tip, wherein the test area is an area of the upper surface of the first bump exposed by the second bump.