Power Semiconductor Chip Dual Metal Layer High Voltage Handling
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Solution Overview
Problem
Current power semiconductor chips face challenges in efficiently managing high voltage and frequency switching due to limitations in their metal layer configurations and manufacturing processes, which affect their performance and reliability in applications like DC-DC converters and motor controllers.
Innovation Solution
The implementation of a power semiconductor chip design with two metal layers on one face, where the second metal layer is electrically insulated from the power transistor circuit, allowing for a stacked configuration of additional semiconductor chips and improved thermal management through external contact elements, enhancing the chip's ability to handle high voltages and frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single metal layer configuration is used on the power semiconductor chip, then the manufacturing process is simpler, but the chip cannot efficiently handle high voltages and frequencies
Solution Approach 1:
The single metal layer is segmented into two distinct metal layers (first metal layer and second metal layer) with different functions. The first metal layer is electrically connected to the power transistor circuit for signal and power transmission, while the second metal layer is electrically insulated and serves as a reference potential or shielding layer, enabling high voltage and frequency handling capabilities.
Solution Approach 2:
The invention transitions from a single-plane metal configuration to a multi-layer vertical structure. By stacking the second metal layer above the first metal layer with electrical insulation between them, the design adds a vertical dimension that enables high voltage isolation and frequency switching capabilities without increasing lateral footprint.
2Reliability
If additional metal layers are added to improve voltage and frequency handling, then the chip's performance increases, but the manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: first forming the metal layer with transistor circuits, then adding a separate second metal layer with electrical insulation. This segmentation allows each layer to be optimized and manufactured independently using standard semiconductor fabrication techniques, reducing overall manufacturing complexity despite the multi-layer structure.
3Temperature
If a stacked configuration of additional semiconductor chips is implemented, then thermal dissipation is improved, but the device structure becomes more complex
Solution Approach 1:
The invention utilizes the vertical dimension by stacking additional semiconductor chips above the second metal layer. This vertical stacking arrangement improves thermal dissipation by providing additional heat sink surfaces and thermal pathways in the vertical direction, while the standardized layer structure keeps the overall device complexity manageable.
Data Source
AI summary
A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.