Semiconductor Chip Pad Structure for Edge Bump Non-Wet Reduction

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Solution Overview

Problem

In flip chip semiconductor packages, the edge portions of semiconductor chips are vulnerable to non-wet phenomena due to warpage caused by differences in thermal expansion coefficients between the chip and the printed circuit board, leading to unstable joint quality and increased risk of non-wet defects during bonding.

Innovation Solution

A semiconductor chip design featuring a dualized pad structure with a center pad and an edge pad of differing shapes, where the edge pad is disposed on the semiconductor substrate to reduce warpage effects, enhancing the contact area and stability of connection bumps, thereby minimizing non-wet risks and joint defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a flip chip package structure with bumps is used to minimize electrical signal transmission path, then electrical characteristics are improved, but joint stability of bumps becomes critical and vulnerable to non-wet phenomena due to warpage

Engineering Contradiction:
Improveelectrical signal transmission speedVSAvoidjoint stability of bumps
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies local quality by creating different pad structures at different locations on the chip. Center pads have a first structure while edge pads have a second structure, allowing each region to be optimized for its specific function and stress conditions during bonding

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses asymmetry by making the edge pad shape different from the center pad shape. This asymmetric design compensates for warpage effects that occur during the bonding process, ensuring that connection bumps at edge portions maintain proper contact with pads despite thermal expansion differences

Inventive Principle:
Principle #4Asymmetry

2Area of stationary object

If edge portions of semiconductor chip are used for mounting, then chip area utilization is improved, but non-wet risk increases due to warpage phenomenon caused by thermal expansion coefficient difference

Engineering Contradiction:
Improvechip area utilizationVSAvoidnon-wet risk at edge portions
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent implements local quality by providing edge pads with a specific second shape that differs from center pads. This localized structural adaptation at edge portions compensates for the warpage effects and thermal expansion issues specific to those regions, reducing non-wet risk while maintaining high chip area utilization

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent applies preliminary anti-action by pre-designing the edge pad shape to counteract the anticipated warpage effects during bonding. The asymmetric edge pad structure is configured in advance to compensate for thermal expansion coefficient differences, preventing non-wet phenomena before they occur

Inventive Principle:
Principle #9Preliminary anti-action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The dualized pad design effectively reduces the occurrence of non-wet defects and improves joint stability by increasing the contact area between pads and connection bumps, even under conditions of warpage, ensuring reliable electrical connections and mechanical integrity in semiconductor packages.

Implementation Method 1

a first connection bump that connects the first bump pad to an external device

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

a warpage phenomenon caused by a difference in thermal expansion coefficient between the semiconductor chip and the printed circuit board

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20240170429A1Semiconductor chip and semiconductor package including the same
Publication Date: 2024.05.23 SAMSUNG ELECTRONICS CO LTD
  • US20240170429A1 patent drawing
  • US20240170429A1 patent drawing
  • US20240170429A1 patent drawing

AI summary

A semiconductor chip includes a semiconductor substrate that includes an upper surface and a lower surface opposite to the upper surface, a center pad disposed on a center portion of the upper surface and an edge portion disposes on an outer portion of the upper surface; a wiring structure that includes a wiring insulating layer disposed on a lower surface of the semiconductor substrate and a wiring pattern disposed in the wiring insulating layer and electrically connected to the semiconductor substrate; a first bump pad disposed on a first surface of the wiring structure and electrically connected to the wiring pattern; and a first connection bump that connects the first bump pad to an external device. The center pad has a regular octagon shape, and the edge pad has an extended octagon shape formed by extending squares from four non-continuous sides of a regular octagon.