Semiconductor Chip Electrical Connection Structure for High-Density Packaging
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Solution Overview
Problem
Conventional flip-chip and wire-bonding semiconductor packaging techniques face challenges with miniaturized IC areas and high-density leads, leading to alignment issues, increased fabrication costs, and reduced reliability due to complex processes and inaccurate molding, which complicates integration and flexibility in design changes.
Innovation Solution
A semiconductor chip electrical connection structure is developed, where conductive bumps are formed on electrode pads, and a dielectric layer is applied and partially removed to expose these bumps, allowing for the formation of electrical connection pads that are electrically connected to the conductive bumps, enabling direct outward electrical extension and simplifying the fabrication process by integrating chip carrier and package fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pad pitch is decreased to accommodate high-density leads, then the packaging density is improved, but the alignment precision deteriorates due to the insulating protective layer covering the pads
Solution Approach 1:
The patent applies preliminary action by forming protruding conductive structures (such as solder bumps or conductive adhesive structures) on the electrode pads before mounting the semiconductor chip. These protruding structures extend beyond the insulating protective layer, ensuring that even with decreased pad pitch, the conductive connection points remain accessible and alignable with the corresponding contact pads on the substrate, thus maintaining alignment precision while achieving high packaging density.
2Manufacturing precision
If the stencil opening size is reduced to match smaller pad pitch, then the manufacturing precision is improved, but the ease of manufacture deteriorates due to difficulty in depositing solder material
Solution Approach 1:
The patent forms protruding conductive structures on the electrode pads before the stencil printing process. These pre-formed structures serve as ready-made receptacles for the solder paste, allowing the stencil openings to be larger and easier to manufacture while still achieving precise alignment. The solder paste is deposited into these protruding structures rather than through extremely small stencil openings, significantly improving the ease of manufacture.
Solution Approach 2:
The patent transitions from a two-dimensional pad surface to a three-dimensional protruding conductive structure. By adding the vertical dimension with protruding structures, the effective target area for solder deposition is increased, allowing larger stencil openings to be used while maintaining precise alignment. This dimensional change resolves the conflict between precision and manufacturability.
3Quantity of substance
If the contact area between the insulating protective layer and the circuit board is reduced to accommodate finer pitch, then the packaging density is improved, but the reliability deteriorates due to weakened adhesion
Solution Approach 1:
The patent applies preliminary action by forming protruding conductive structures on the electrode pads before chip mounting. These protruding structures provide additional surface area and mechanical interlocking capability for the solder joints, compensating for the reduced contact area of the insulating protective layer. This ensures that adhesion reliability is maintained even when pad pitch is decreased to achieve higher packaging density.
4Reliability
If the conventional flip-chip packaging technique is used with solder bumps, then the electrical performance is improved, but the device complexity increases due to multiple fabrication processes
Solution Approach 1:
The patent merges the chip fabrication process with the substrate mounting process by forming the protruding conductive structures on the electrode pads during the chip manufacturing stage. This integration eliminates the need for separate post-fabrication bump formation processes and simplifies the overall fabrication flow, reducing device complexity while maintaining the electrical performance benefits of direct solder bump connections.
Data Source
AI summary
A semiconductor chip electrical connection structure includes electrode pads formed on a surface of a semiconductor chip, wherein the semiconductor chip is mounted via another surface thereof on a carrier; a plurality of conductive bumps formed on the electrode pads respectively, and exposed from a dielectric layer applied on the semiconductor chip and the carrier; and a plurality of electrical connection pads formed on the dielectric layer and electrically connected to the conductive bumps exposed from the dielectric layer so as to provide outward electrical extension for the semiconductor chip via the electrical connection pads.