Semiconductor Chip Electrode Design for Dicing Shock Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Miniaturized and highly integrated semiconductor chips face challenges during wire bonding and electrical property inspections due to shock damage from electrode pads, especially when formed on active areas or using low-k interlayer insulating films, leading to chipping and cracking during dicing.
Innovation Solution
A semiconductor wafer design where projecting electrodes are selectively formed only on electrode portions in semiconductor chip areas by electroless plating, with an insulating film covering the scribe area to prevent damage during inspections and dicing, allowing for the use of different metal layers and lattice-like insulators to minimize stress and chipping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If projecting electrodes are formed on all electrode portions including scribe area, then shock resistance during bonding is improved, but chipping and cracking occur during dicing
Solution Approach 1:
The patent applies different treatments to different regions: projecting electrodes are formed only on electrode portions in semiconductor chip areas, while electrode portions in scribe areas are covered with insulating films. This local differentiation allows shock resistance where needed while preventing chipping during dicing in the scribe area.
2Productivity
If electrode pads are formed on active areas to increase terminal count, then integration degree is improved, but shock damage to underlying structures occurs
Solution Approach 1:
The patent forms projecting electrodes selectively on electrode portions located on active areas, providing shock resistance precisely where the electrode pads are formed. The insulating film coverage on scribe area electrode portions prevents damage while allowing the active area electrode portions to benefit from enhanced shock resistance.
3Speed
If low-k interlayer insulating film is used to reduce capacitance, then speed is improved, but shock resistance deteriorates
Solution Approach 1:
The patent forms projecting electrodes on electrode portions before bonding occurs, creating a protective structure in advance. These projecting electrodes act as a cushioning layer that absorbs shock during wire bonding or inner lead bonding, protecting the low-k interlayer insulating film and underlying structures from damage.
4Measurement precision
If probe contact inspection is performed on electrode pads, then measurement is achieved, but shock damage occurs to fragile structures
Solution Approach 1:
The patent provides shock resistance at electrode portions through projecting electrodes while covering scribe area electrode portions with insulating films. This allows probe contact inspection to be performed on protected electrode portions without causing shock damage to the low-k interlayer insulating film or active elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to electrode pads and underlying structures during bonding and inspections, reduces chipping and cracking during dicing, and maintains the integrity of semiconductor chips, even in highly integrated designs.
Implementation Method 1
projecting electrodes are selectively formed only on electrode portions in semiconductor chip areas by electroless plating
Data Source
AI summary
A semiconductor wafer 10 has a plurality of semiconductor chip areas 10a and a scribe area 10b, each of the semiconductor chip areas 10a having semiconductor elements and electrode pads (electrode portions) 16a electrically connected to the respective semiconductor elements, the scribe area 10b having monitor elements and electrode pads (electrode portions) 16b electrically connected to the monitor elements, wherein projecting electrodes 18 are selectively formed only on the respective electrode pads 16a in the semiconductor chip areas 10a by electroless plating. Thus, for example, the electrode pads 16b are covered with an insulating film 14.