Semiconductor Chip Electrode Pad Segmentation for Package Versatility
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Solution Overview
Problem
Conventional wafer level CSP techniques face challenges in connecting wires from electrode pads to external connection terminals, especially when these terminals are disposed in the peripheral and central parts of the semiconductor chip, leading to increased development costs and time due to the need for dedicated semiconductor chips with specific designs for different package types.
Innovation Solution
A semiconductor chip with electrode sections on its main surface, including at least one first electrode section in the peripheral part and one second electrode section in the inner part, both electrically connected, allowing signals to be inputted or outputted from either section, enabling versatility across various semiconductor packages, including CSPs and wafer level CSPs, without the need for separate design specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If electrode pads are disposed only in the peripheral part of the semiconductor chip for wire bonding, then wire length is shortened and wire deformation is prevented, but external connection terminals cannot be disposed in the peripheral part when needed, limiting package design flexibility
Solution Approach 1:
The patent makes electrode pads universally usable for both wire bonding and direct connection to external terminals. By disposing electrode pads in both peripheral and inner regions, the same chip design can accommodate different package types (CSP with wire bonding and wafer level CSP with direct terminals), eliminating the need for dedicated chip designs for each package type.
Solution Approach 2:
The patent segments the electrode pad disposal regions into peripheral parts (for wire bonding) and inner parts (for direct terminal connection). This segmentation allows different regions to serve different functions, enabling the chip to adapt to various package configurations without compromising wire bonding performance or terminal accessibility.
2Quantity of substance
If external connection terminals are disposed in the peripheral part of the semiconductor chip, then signal density is increased, but wires cannot be drawn from electrode pads to external terminals due to overlapping positions
Solution Approach 1:
The patent separates electrode pad disposal into peripheral regions and inner regions. Peripheral electrode pads are dedicated to wire bonding, while inner electrode pads are dedicated to direct terminal connection. This segmentation eliminates the conflict where external terminals would overlap with peripheral electrode pads, allowing high signal density without compromising wire connection feasibility.
3Productivity
If a single semiconductor chip design is used for both CSP and wafer level CSP, then development cost and time are reduced, but the chip must accommodate conflicting requirements for electrode pad disposal
Solution Approach 1:
The patent creates a universal chip design that can serve both CSP and wafer level CSP applications. By disposing electrode pads in both peripheral and inner regions, the same chip can be used for wire bonding (CSP) or direct terminal connection (wafer level CSP), significantly reducing development cost and time while managing electrode pad configuration complexity through systematic spatial arrangement.
Data Source
AI summary
In the peripheral part of a semiconductor chip, third electrode pads for wire bonding and plate wiring and first electrode pads dedicated to wire bonding are provided. On the other hand, second electrode pads dedicated to plate wiring are provided on an inner part away from the edge of the semiconductor chip. Further, the first and second electrode pads are connected via metal bypass layers, respectively. In the case of wire bonding, the first and third electrode pads are used and the third electrode pads are encapsulated with an insulating layer. Further, in the case of plate wiring, the second and third electrode pads are used and the first electrode pads are covered with an insulating layer. This realizes a semiconductor chip which has great versatility and which can be used in semiconductor packages of various types.