Semiconductor Chip Embedding in Universal Leadframe Cavities
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Solution Overview
Problem
Current semiconductor chip packaging technologies face challenges in efficiently integrating semiconductor chips of different sizes and forms, particularly in achieving high-density, compact designs while maintaining accurate positioning and electrical connectivity.
Innovation Solution
A method involving a core layer package embedding process, which includes lamination, selective etching, diffusion soldering, and microvia formation, allows for the accurate embedding and electrical connection of semiconductor chips of varying thicknesses on a conductive foil carrier, enabling the creation of a package with multiple chips on the same level without requiring precise leadframe cavities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional packaging technologies are used, then chip integration is achieved, but manufacturing complexity and cost increase when integrating chips of different sizes and forms
Solution Approach 1:
The leadframe structure is designed with universal cavities that can accommodate multiple chip types (different sizes, forms, and thicknesses) using the same packaging process. The cavity system serves multiple functions: mechanical support, electrical connection, and planarization for various chip configurations without requiring different packaging approaches.
Solution Approach 2:
The patent varies cavity parameters (depth, width, positioning) within a standardized leadframe structure to accommodate different chip thicknesses and sizes. By adjusting these parameters while maintaining the overall packaging process, the system achieves versatility without proportionally increasing manufacturing complexity.
2Volume of moving object
If high-density integration is pursued, then compact design is achieved, but positioning accuracy and electrical connectivity become more difficult to maintain
Solution Approach 1:
Cavities are pre-formed in the leadframe structure with precise dimensions and positions before chip attachment. This preliminary preparation ensures that when chips are placed in the cavities, positioning accuracy is maintained even in high-density configurations, as the cavities act as pre-positioned receptacles that guide chip placement.
Solution Approach 2:
Multiple chips of varying sizes are arranged within the leadframe structure, with smaller chips potentially positioned within or adjacent to larger cavity structures. This nested arrangement enables high-density integration while maintaining individual chip positioning accuracy through the hierarchical cavity system.
3Adaptability or versatility
If chips of different thicknesses are integrated, then design flexibility is improved, but achieving planar surfaces and accurate connections becomes more challenging
Solution Approach 1:
Each cavity is customized with specific depth and structural characteristics matched to the chip it accommodates. This local adaptation allows chips of different thicknesses to be integrated while maintaining overall surface planarity, as each chip sits at the appropriate depth within its dedicated cavity rather than requiring all chips to be the same thickness.
Solution Approach 2:
The leadframe cavity structure serves as a master template or copy that replicates the required positioning and support geometry for different chip types. By using the cavity design as a reusable pattern that can be adapted to various chip thicknesses, the system maintains manufacturing precision across diverse chip configurations.
4Manufacturing precision
If precise leadframe cavities are manufactured for each chip type, then positioning accuracy is improved, but manufacturing time and cost increase
Solution Approach 1:
A single leadframe structure with a set of pre-formed cavities serves as a universal platform for multiple chip types. This universal approach eliminates the need to manufacture different cavity sets for different chips, thereby maintaining positioning accuracy through the cavity system while significantly improving production efficiency by using one standardized manufacturing process for all chip integrations.
Solution Approach 2:
The leadframe is segmented into multiple discrete cavities, each capable of holding a different chip type. This segmentation allows the single leadframe structure to handle multiple chip configurations simultaneously, maintaining precision through the segmented cavity design while improving productivity by processing multiple chip types through one unified manufacturing flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach facilitates high-volume, low-cost production of semiconductor packages with improved planarity and reduced design complexity, allowing for the integration of chips with different thicknesses while maintaining accurate electrical connections and surface quality.
Implementation Method 1
a first electrically conductive layer arranged over the first semiconductor chip and electrically coupled to the first contact pad
Implementation Method 2
A method involving a core layer package embedding process, which includes lamination, selective etching, diffusion soldering, and microvia formation
Implementation Method 3
diffusion soldering, and microvia formation, allows for the accurate embedding and electrical connection of semiconductor chips
Data Source
AI summary
A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.