Semiconductor Chip Singulation via Chemical Etching
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Solution Overview
Problem
Blade dicing methods for semiconductor substrates result in longer dicing times, low shock resistance, and low flexural strength due to right-angled corners and fine cracking at chip ends, which are not effectively addressed by existing technologies.
Innovation Solution
A method involving the formation of etching masks with specific shapes on semiconductor substrates, followed by chemical etching using a precious metal catalyst to create grooves and trenches, which increases mechanical strength and reduces dicing time by anisotropically removing exposed regions, resulting in singulated chips with improved corner shapes and reduced cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If blade dicing is used to singulate semiconductor substrates, then the substrate can be cut into chips, but the dicing time becomes longer in proportion to the number of dicing grooves
Solution Approach 1:
The patent replaces the mechanical blade dicing system with a chemical etching system. Instead of using a rotating blade to physically cut the substrate, the invention uses chemical etching solutions to remove material and form dicing grooves, thereby eliminating the time-consuming mechanical cutting process while maintaining effective chip singulation
Solution Approach 2:
The patent changes the fundamental parameter of the dicing process from mechanical force to chemical reaction. By controlling etching parameters such as solution composition, temperature, and exposure time, the process achieves rapid material removal without the mechanical constraints of blade dicing, significantly reducing dicing time
2Ease of manufacture
If blade dicing is used to singulate semiconductor substrates, then chips can be obtained, but the chips have right-angled corner portions and low shock resistance
Solution Approach 1:
The patent applies curvature by forming rounded corner portions on chips through chemical etching. The etching process naturally creates curved profiles at the corners and edges of dicing grooves, eliminating the sharp right-angled corners produced by mechanical blade dicing. This curvature distributes stress more evenly, significantly improving shock resistance while maintaining effective chip separation
3Ease of manufacture
If blade dicing is used to singulate semiconductor substrates, then chips can be obtained, but fine cracking occurs at end portions of the chip
Solution Approach 1:
The patent replaces the mechanical blade dicing system with a chemical etching system to eliminate fine cracking. The chemical etching process removes material through dissolution rather than mechanical force, preventing the formation of micro-cracks at chip end portions that occur during mechanical cutting, thereby maintaining chip integrity and reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the mechanical strength and shock resistance of semiconductor chips by forming rounded or polygonal corners, reducing dicing time, and minimizing cracking, while maintaining the reliability of the chip's operation through chemical etching without physical damage.
Implementation Method 1
chemical etching using a precious metal catalyst to create grooves and trenches, which increases mechanical strength and reduces dicing time by anisotropically removing exposed regions
Data Source
AI summary
A method of manufacturing a semiconductor chip according to an embodiment includes forming on a semiconductor substrate a plurality of etching masks each including a protection film to demarcate a plurality of first regions of the substrate protected by the plurality of etching masks and a second region as an exposed region of the substrate, and anisotropically removing the second region by a chemical etching process to form a plurality of grooves each including a side wall at least partially located in the same plane as an end face of the etching mask and a bottom portion reaching a back surface of the substrate, thereby singulating the semiconductor substrate into a plurality of chip main bodies corresponding to the plurality of first regions.