Stacked Semiconductor Chip Grouping via Fuse Signals

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Solution Overview

Problem

In semiconductor apparatuses with stacked chips, if one chip fails, the entire stack becomes unusable, leading to inefficiency and productivity loss due to the sequential addressing method that assumes all chips are functional.

Innovation Solution

A semiconductor apparatus and method that generates individual chip designating codes, enables chip activation signals based on matching codes, and uses fuse signals to select and activate functional chips, allowing the remaining chips to be used even if one has failed, by dividing activation signals into groups and selecting them based on test fuse signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If sequential addressing method is used to assign addresses to stacked chips, then the addressing system is simple and easy to implement, but the entire stack becomes unusable if one chip fails

Engineering Contradiction:
Improveaddressing system complexityVSAvoidstack usability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the chip stack into multiple independently addressable groups using fuse signals. Each group can be selectively activated, so that if one chip fails, other groups remain functional. This segments the addressing space into isolated regions that can operate independently.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the addressing parameter by introducing fuse-based group selection that modifies how addresses are interpreted. Instead of sequential addressing across all chips, the system uses fuse signals to change the addressing mode to skip over failed chips and activate only functional groups.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If all stacked chips are assumed to be functional, then the productivity and efficiency are maximized, but the system cannot tolerate any chip failures

Engineering Contradiction:
Improvechip utilization efficiencyVSAvoidfailure tolerance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary actions by setting fuse signals during manufacturing to pre-define groups of chips and their activation conditions. This preliminary configuration enables the system to automatically handle failures by activating appropriate groups without requiring runtime diagnostics or reconfiguration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent provides beforehand cushioning by creating redundant chip groups that can compensate for failures. The fuse-based grouping system pre-prepares alternative chip configurations so that when a failure occurs, the system has already-established backup groups ready to be activated.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If fuse signals are used to select and activate functional chips, then the system can tolerate chip failures, but the device complexity increases

Engineering Contradiction:
Improvefailure toleranceVSAvoidcontrol logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements self-service by using fuse signals that are automatically read and processed by the existing control logic without requiring additional complex control mechanisms. The fuse configuration itself serves as the selection mechanism, eliminating the need for separate control circuits to identify and activate functional chips.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9519020B2Semiconductor apparatus and chip selecting method thereof
Publication Date: 2016.12.13 SK HYNIX INC
  • US9519020B2 patent drawing
  • US9519020B2 patent drawing
  • US9519020B2 patent drawing

AI summary

A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.