3D Semiconductor Chip ID Assignment via Through-Silicon Vias
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Solution Overview
Problem
Current 3D semiconductor apparatuses face challenges in efficiently assigning IDs to multiple chips due to complex wiring and packaging complexities, especially when using misaligned step-like chip stacking and limited chip selection capabilities.
Innovation Solution
The semiconductor apparatus employs a system of through-silicon vias (TSVs) and chip ID generation units to generate and transmit chip ID signals, allowing for efficient chip selection through serial connections and redistribution layers, enabling precise activation of individual chips within the stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If chip selection pins are additionally provided for each chip to enable chip selection, then chip selection capability is improved, but chip footage is reduced and device complexity increases
Solution Approach 1:
The patent merges the chip selection function with the existing TSV structure by routing selection signals through shared vertical interconnect paths. Multiple chips share common TSVs for receiving selection signals, eliminating the need for separate selection pins on each chip surface while maintaining individual chip selectability through signal timing and encoding schemes.
Solution Approach 2:
The patent transitions chip selection from a 2D surface-mounted pin approach to a 3D volumetric approach using TSVs. Selection signals are delivered through the vertical dimension via TSVs that penetrate through multiple chip layers, allowing chip selection without consuming valuable surface footage on any individual chip.
2Adaptability or versatility
If chip selection pins are additionally provided for each chip, then chip selection capability is improved, but device complexity and wiring complexity increase
Solution Approach 1:
The patent combines multiple functions into the TSV structure: power delivery, data transmission, and chip selection signaling all share the same vertical interconnect pathways. This consolidation eliminates separate wiring for selection pins and reduces overall circuit complexity while maintaining full chip selection capability.
Solution Approach 2:
The TSVs are designed as universal interconnect structures that can carry multiple types of signals (power, data, control) simultaneously or sequentially. This multi-functionality reduces the need for dedicated wiring for each function, simplifying the overall circuit design while enabling chip selection across multiple chips.
3Productivity
If chips are stacked in a misaligned step-like shape to accommodate multiple chips, then degree of integration is improved, but packaging complexity increases
Solution Approach 1:
The patent segments the TSV routing into modular units that can be independently configured for each chip in the stack. This segmentation allows flexible accommodation of misaligned chip positions while maintaining standardized TSV connection patterns, simplifying the packaging process despite the complex 3D arrangement.
4Productivity
If TSVs are used to electrically connect multiple chips, then degree of integration is improved, but ID assignment complexity increases
Solution Approach 1:
The patent implements preliminary action by pre-configuring TSV routing patterns and signal timing schemes during the design phase to automatically provide unique identification paths for each chip. This preliminary configuration eliminates the need for complex runtime ID assignment logic, reducing operational complexity while maintaining high integration.
Data Source
AI summary
A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.