Semiconductor Chip Insulation Layer for Wire Bonding Short Prevention

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Solution Overview

Problem

Electrical shorts often occur between bonding wires and semiconductor chips due to the wires making contact with the active surface corners during mounting on lead frames or BGA-specific printed circuit boards.

Innovation Solution

A method involving the formation of an insulation layer over the semiconductor chip regions, with a photoresist pattern used as an etching mask to expose and isolate the scribing lanes, preventing bonding wires from contacting the chip edges, and extending beyond the chip edges to protect the integrated circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding wires are used to electrically connect electrode pads to substrate pads, then electrical connections are established, but electrical shorts occur when wires contact corners of the active surface of the semiconductor chip

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidelectrical short between bonding wire and chip

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

An insulation layer is introduced as an intermediary substance between the bonding wire and the semiconductor chip. This insulation layer, formed by depositing dielectric material over the active surface and extending to the corners, prevents direct contact between the conductive bonding wire and the chip corners, thereby eliminating the electrical short problem while maintaining the electrical connection function.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The insulation layer is formed in advance before the bonding wire deposition process. By pre-coating the chip corners and active surface with insulating material, the potential harmful contact between bonding wires and chip corners is prevented before the bonding process occurs, thus avoiding electrical shorts from the outset.

Inventive Principle:

Principle #9Preliminary anti-action

2Object-affected harmful factors

If the insulation layer extends beyond the edge of the semiconductor chip, then protection against electrical shorts is improved, but the chip size and packaging area increase

Engineering Contradiction:

Improveelectrical short preventionVSAvoidchip area

Core Design Contradiction:

Object-affected harmful factorsVSArea of moving object

Solution Approach 1:

The insulation layer is selectively extended only to the corners and edges of the semiconductor chip where electrical shorts are most likely to occur, rather than uniformly increasing the chip area. This localized extension provides targeted protection at critical locations while minimizing the overall area increase, thus resolving the contradiction between short prevention and area minimization.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively prevents electrical shorts between the semiconductor chip and bonding wires, simplifying the process and ensuring reliable electrical connections during chip packaging.

Implementation Method 1

A photoresist pattern is used as an etching mask to expose the scribing lane

Methodology Applied

Scientific EffectPhotolithography: Photopolymerisation

Data Source

PatentUS8178393B2Semiconductor package and manufacturing method thereof

Publication Date: 2012.05.15 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip.