Semiconductor Chip Insulation Layer Stress Relief
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Solution Overview
Problem
Conventional semiconductor devices experience reliability issues due to peeling of the resin layer from the semiconductor chip caused by thermal expansion and contraction differences between silicon and resin materials, leading to stress and dimensional changes, particularly at the corner portions.
Innovation Solution
A semiconductor device manufacturing method involving the formation of a first insulation layer covering the semiconductor chips and a scribe region, with a second insulation layer exposing the substrate cutting position, and a metal layer formation for internal and external connection terminals, which reduces stress by preventing the resin layer from being cut during substrate cutting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a resin layer is formed to cover the semiconductor chip, then the semiconductor device achieves chip size package configuration, but the resin layer peels from the semiconductor chip due to thermal expansion differences
Solution Approach 1:
The patent applies preliminary action by forming the insulation layer covering the scribe region and cutting positions before the final substrate cutting step. This ensures that the insulation layer is already in place to provide stress relief before the mechanical cutting process occurs, preventing peeling from the outset rather than attempting to fix it afterward.
Solution Approach 2:
The patent introduces an insulation layer as an intermediary substance between the resin layer and the semiconductor chip at the cutting regions. This intermediate layer acts as a buffer that absorbs and distributes the thermal stress and mechanical stress, preventing direct stress concentration at the resin-chip interface and thereby preventing peeling.
2Productivity
If the substrate is cut to divide into semiconductor chips, then individual devices are produced, but the resin layer and insulation layer peel at the cutting positions
Solution Approach 1:
The patent forms the insulation layer covering the scribe region and cutting positions before the final substrate cutting step. This preliminary formation ensures that the insulation layer is already in place to provide stress relief before the mechanical cutting process occurs, preventing peeling from the outset rather than attempting to fix it afterward.
Solution Approach 2:
The patent introduces an insulation layer as an intermediary substance between the resin layer and the semiconductor chip at the cutting regions. This intermediate layer acts as a buffer that absorbs and distributes the thermal stress and mechanical stress, preventing direct stress concentration at the resin-chip interface and thereby preventing peeling.
3Ease of manufacture
If conventional manufacturing steps are followed, then standard semiconductor devices are produced, but peeling occurs requiring additional preventive steps
Solution Approach 1:
The patent forms the insulation layer covering the scribe region and cutting positions before the final substrate cutting step. This preliminary formation ensures that the insulation layer is already in place to provide stress relief before the mechanical cutting process occurs, preventing peeling from the outset rather than attempting to fix it afterward.
Solution Approach 2:
The patent introduces an insulation layer as an intermediary substance between the resin layer and the semiconductor chip at the cutting regions. This intermediate layer acts as a buffer that absorbs and distributes the thermal stress and mechanical stress, preventing direct stress concentration at the resin-chip interface and thereby preventing peeling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and yield of semiconductor devices by minimizing peeling and stress effects, improving the bonding strength between layers and reducing manufacturing costs.
Implementation Method 1
when the semiconductor device 100 is heated or cooled, the respective layers 101, 103 and 106 expands or contracts in accordance with respective materially intrinsic coefficient of thermal expansion
Implementation Method 2
when the semiconductor device 100 is heated or cooled, the respective layers 101, 103 and 106 expands or contracts in accordance with respective materially intrinsic coefficient of thermal expansion
Data Source
AI summary
A method for manufacturing a semiconductor device has preparation step of preparing a semiconductor substrate having a plurality of semiconductor chip formation regions and a scribe region arranged between the plurality of the semiconductor chip formation regions and including a substrate cutting position, a semiconductor chip formation step of forming semiconductor chips having electrode pads on the plurality of semiconductor chip formation regions, a first insulation layer formation step of forming a first insulation layer on the semiconductor chips and the scribe region of the semiconductor substrate, a second insulation layer formation step of forming a second insulation layer on the first insulation layer except for a region corresponding to the substrate cutting position, and a cutting step of cutting the semiconductor substrate at the substrate cutting position.