Semiconductor Chip Inversion for Thermal Management and Upper-Side Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for producing semiconductor components are inadequate for chips requiring electrical or optical contacting on the upper side and suffer from inadequate heat dissipation.
Innovation Solution
A method involving a planar carrier with a continuous recess, where a semiconductor arrangement with electrically or optically active regions on its underside is encapsulated and then thinned to create a common plane with the carrier, allowing for efficient heat dissipation and access to the upper side for optical or electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the semiconductor chip is cast in a casting compound with the underside on an adhesive film, then the semiconductor chip is fixed to the carrier material, but the upper side of the semiconductor chip becomes inaccessible for electrical or optical contacting
Solution Approach 1:
The patent inverts the conventional mounting approach by flipping the semiconductor chip after bonding, so that the underside (with active regions) faces upward. This inversion makes the upper side accessible for contacting while maintaining the bonding integrity of the underside to the carrier.
Solution Approach 2:
The patent introduces a recess in the carrier material that accommodates the semiconductor chip in a flipped orientation. This dimensional change in the carrier structure enables the chip to be mounted with its active side facing upward, providing access from above while maintaining mechanical support.
2Ease of manufacture
If the semiconductor chip is mounted with active regions on the underside, then bonding is simplified, but heat dissipation becomes insufficient
Solution Approach 1:
By inverting the chip orientation so the active side faces upward, the patent enables direct thermal contact between the active regions and the carrier material or heat sink, significantly improving heat dissipation while maintaining bonding simplicity.
Solution Approach 2:
The carrier material serves as a thermal intermediary, conducting heat away from the semiconductor chip's active regions. The recess structure enhances this thermal management function by providing direct thermal pathways from the chip to the carrier.
3Reliability
If the connection points are distributed over a large area on the rewiring layer, then electrical connectivity is improved, but the upper side remains inaccessible for direct contacting
Solution Approach 1:
The patent eliminates the need for extensive rewiring by inverting the chip so that connection points can be directly accessed on the upper side. This direct access improves reliability by reducing the number of intermediate connection layers while maintaining electrical connectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables efficient heat dissipation and facilitates electrical or optical connections on the upper side of semiconductor components, addressing the limitations of existing methods by providing a semiconductor system with improved thermal management and accessibility.
Implementation Method 1
The semiconductor arrangement is encapsulated with an encapsulation compound in such a way that the semiconductor arrangement is bonded to the carrier
Implementation Method 2
The semiconductor system is then thinned out by grinding from above in such a way that a top side of the carrier and a top side of the semiconductor arrangement run in a common plane
Data Source
Figure 1~7
Figure 8~10
Figure 11~13
AI summary
The invention relates to a method for producing a semiconductor component (27). The proposed method comprises the provision of a planar support (4) comprising an upper face (6) and a lower face (7), the support (4) having a continuous opening (5) running between the upper face (6) and the lower face (7). A semiconductor arrangement (8) is provided in a further step. The semiconductor arrangement (8) has a semiconductor chip (10) with electrically and/or optically active regions (12) on its underside (11). The semiconductor arrangement (8) is then positioned in the opening (5), such that a lower face (9) of the semiconductor arrangement (8) and the lower face (7) of the support (4) run on a common plane. The semiconductor arrangement (8) is subsequently potted using a potting compound (17), such that the semiconductor arrangement (8) is bonded to the support (4). The semiconductor arrangement (8) forms a semiconductor system (18) together with the support (4) and the potting compound (17). Finally, the semiconductor system (18) is thinned by milling from above, such that the upper face (6) of the support and an upper face (22) of the semiconductor arrangement (8) run on a common plane.