Semiconductor Chip Laminate Silicon Support Warping

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Solution Overview

Problem

Thinning semiconductor chips for stacking in semiconductor devices leads to reduced rigidity and warping, causing connection failures and reliability issues, especially when using silicon vias, which worsens with stacked structures.

Innovation Solution

A semiconductor device design that incorporates a silicon substrate as a support member for the chip laminate, providing structural rigidity and thermal expansion matching, along with a resin structure to prevent warping, and a wiring layer for connectivity, allowing for effective stacking and packaging while minimizing size and thickness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor chips are thinned to achieve miniaturization and stacking, then device density increases, but chip rigidity decreases causing warping and connection failures

Engineering Contradiction:
Improvechip thicknessVSAvoidchip rigidity
Core Design Contradiction:
Volume of moving objectVSStrength

Solution Approach 1:

A support member is introduced as an intermediary component between the thinned semiconductor chips and the substrate. This support member has a larger area than the chip laminate and provides mechanical reinforcement, preventing warping while allowing the chips to remain thin. The support member acts as a mediator that compensates for the lost rigidity without requiring thicker chips.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs a composite structure combining the semiconductor chips, support member, and substrate. The support member is made of a material that can be cut and ground easily while providing sufficient mechanical strength. This composite approach allows each component to contribute its optimal properties: thin chips for density, support member for rigidity, and substrate for mounting.

Inventive Principle:
Principle #40Composite materials

2Productivity

If semiconductor chips are stacked to increase device density, then miniaturization is achieved, but warping increases and connection reliability decreases

Engineering Contradiction:
Improvedevice densityVSAvoidconnection reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The support member serves as a stabilizing intermediary that spans across multiple stacked chips. By having a larger area than the chip laminate, it distributes mechanical stresses uniformly across the stack, preventing differential warping that would cause connection failures. This mediator enables reliable stacking by decoupling the density benefit from the warping penalty.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If silicon vias are used to connect stacked semiconductor chips, then vertical connectivity is achieved, but warping of chips markedly increases

Engineering Contradiction:
Improvevertical connectivityVSAvoidchip warping
Core Design Contradiction:
Ease of operationVSShape

Solution Approach 1:

The support member acts as a counteracting intermediary that offsets the warping induced by silicon via formation. The via structure creates localized stress concentrations that warp the chips, but the support member's larger area and appropriate material properties provide a compensating counter-stress, maintaining chip flatness while preserving the vertical connectivity benefit.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The silicon substrate support enhances chip laminate stability, reduces warping, and improves reliability by matching thermal expansion coefficients, facilitating easier cutting and grinding, thus enhancing the overall performance and reliability of the semiconductor device.

Implementation Method 1

The silicon substrate support enhances chip laminate stability, reduces warping, and improves reliability by matching thermal expansion coefficients

Methodology Applied
Scientific EffectThermal expansion coefficient matching: Thermal Expansion

Data Source

PatentUS9595507B2Semiconductor device and method of manufacturing the same
Publication Date: 2017.03.14 KIOXIA CORP
  • US9595507B2 patent drawing
  • US9595507B2 patent drawing
  • US9595507B2 patent drawing

AI summary

According to one embodiment, a semiconductor device includes a laminate including a plurality of semiconductor chips and having a first width, at least part of the semiconductor chips including an electrode extending through the semiconductor chip, the semiconductor chips being stacked and connected to each other via the electrode; a silicon substrate provided on a first surface of the laminate and having a second width larger than the first width; a wiring layer provided on a second surface of the laminate; and a resin provided around the laminate.