Semiconductor Chip Layout Partitioning for Parallel OPC Retargeting
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Solution Overview
Problem
Existing semiconductor chip manufacturing processes face disparities between designed and transferred circuit patterns due to optical proximity and loading effects, leading to inefficiencies in pattern transfer and prolonged turnaround times.
Innovation Solution
A layout method for semiconductor chips that employs restriction rules to limit pattern lengths, partitions layouts into regions, and performs retargeting and optical proximity correction in parallel, ensuring independent processing of each region to improve parallelism and reduce turnaround time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the layout is processed as a single unit for retargeting, then pattern integrity is maintained, but processing time increases and parallelism is reduced
Solution Approach 1:
The layout is divided into multiple unit regions based on design rules that ensure patterns spanning across regions meet length requirements. This segmentation enables parallel retargeting processing of each region while maintaining pattern integrity through reference region inclusion at boundaries.
2Productivity
If the layout is partitioned into multiple regions for parallel processing, then turnaround time is reduced, but pattern integrity may be compromised at region boundaries
Solution Approach 1:
Reference regions are pre-added to unit regions before parallel retargeting processing. These reference regions contain pattern information from adjacent regions, enabling correct retargeting at boundaries while maintaining parallel processing efficiency.
3Manufacturing precision
If retargeting is performed sequentially on the entire layout, then pattern accuracy is ensured, but manufacturing efficiency decreases
Solution Approach 1:
The layout is segmented into unit regions that can be processed independently in parallel. Design rules ensure that patterns requiring continuity across regions are properly handled through reference regions, enabling both parallel processing and pattern accuracy.
4Adaptability or versatility
If the layout uses unrestricted pattern lengths, then design flexibility is maintained, but optical proximity effects cause greater disparity between designed and transferred patterns
Solution Approach 1:
Design rules are established that constrain pattern lengths in unit regions based on optical proximity effect characteristics. These parameter constraints reduce disparity between designed and transferred patterns while maintaining sufficient design flexibility for functional requirements.
Data Source
AI summary
A layout method of a semiconductor chip, includes designing a layout using a restriction rule such that a layout pattern having a length smaller than a first length in a first direction has to have a length smaller than a second length in a second direction, the second direction intersecting the first direction, generating a plurality of unit regions by partitioning the layout in the first direction, generating a plurality of target regions by adding a reference region to a partitioned edge of each of the plurality of unit regions, retargeting the plurality of target regions in parallel, and generating a correction layout by merging the plurality of retargeted target regions.