Semiconductor Chip Mounting via Semi-Curing Resin Opening
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Solution Overview
Problem
Existing semiconductor devices with stacked chip structures face challenges in reducing size due to increased wire length and inability to form electrode pads on all sides, leading to larger device sizes and inhibited size reduction.
Innovation Solution
A method involving a support with a chip mounting region and a peripheral region, where an insulating resin layer is formed in a semi-curing state, and a chip is mounted through a precisely formed opening, allowing for reduced wire length and precise chip placement, enabling smaller device sizes by using a via as an external connecting terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are stacked with shift through insulating bonding layer, then chip mounting is enabled, but device size increases and wire length increases
Solution Approach 1:
The invention transitions from planar chip mounting to three-dimensional stacked mounting. Multiple chips are arranged vertically in stacked positions rather than horizontally on the same plane, utilizing the vertical dimension to reduce the overall device footprint while maintaining mounting functionality.
Solution Approach 2:
The support structure is designed to accommodate multiple chips in a nested stacked configuration. The support includes multiple opening portions arranged in stacked positions, allowing chips to be mounted one above another, with each chip nested within the vertical space occupied by the device rather than requiring horizontal expansion.
2Ease of manufacture
If chips are stacked with shift, then chip mounting is enabled, but wiring length increases
Solution Approach 1:
The support structure provides electrical connection terminals in the vertical dimension through vias that extend through the support thickness. This allows wiring to connect stacked chips vertically through the support rather than requiring long horizontal wires to reach external terminals, significantly reducing total wiring length.
Solution Approach 2:
The support acts as an intermediary structure that provides both mechanical support and electrical connection functionality. The vias formed in the support serve as intermediate connection points between stacked chips, eliminating the need for long external wiring and reducing overall wiring length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the reduction of semiconductor device size by minimizing wire length and enabling precise chip mounting without positional shifts, facilitating the formation of a Chip Size Package (CSP) structure with enhanced connecting properties.
Implementation Method 1
forming an insulating resin layer in a semi-curing state on the plane; completely curing the insulating resin layer after the step (d)
Data Source
AI summary
A method of manufacturing a semiconductor device, includes the steps of: (a) providing a support including a plane having a first region for mounting a chip thereon and a second region provided around the first region; (b) forming an insulating resin layer in a semi-curing state on the plane; (c) forming, on the insulating resin layer, a first opening portion for exposing the first region; (d) fitting a chip in the first opening portion to mount the chip on the first region; and (e) completely curing the insulating resin layer after the step (d).