Semiconductor Chip Package With Laterally Extending Connectors
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Solution Overview
Problem
In electronic systems, converter circuits such as DC/DC, AC/DC, and frequency converters require compact semiconductor chip packages with reduced switching losses and parasitic inductances, which is challenging due to the need for integrated modules with short interconnections on printed circuit boards.
Innovation Solution
A semiconductor chip package is fabricated using a carrier with semiconductor chips, encapsulation layers, metallization layers, and external connectors, where via connections and metallization layers form electrical connections between chips, and a second encapsulation layer encapsulates the connectors, enhancing thermal dissipation and reducing interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If components are mounted as individual components on a printed circuit board, then ease of manufacture and assembly is improved, but space consumption increases and interconnection length increases leading to higher switching losses and parasitic inductances
Solution Approach 1:
The patent merges multiple individual components (semiconductor chips, driver chips, passive components) and their interconnections into a single integrated semiconductor chip package. This consolidation reduces the overall space required while maintaining manufacturability through standardized packaging processes. The components are mounted on a carrier within the package, allowing compact arrangement that minimizes both footprint and interconnection lengths.
Solution Approach 2:
The patent transitions from planar mounting on a printed circuit board to three-dimensional integration within a package. Multiple layers of components are stacked vertically on the carrier, with interconnections routed through via holes between layers. This vertical arrangement significantly reduces the horizontal footprint while keeping assembly processes manageable through established semiconductor packaging techniques.
2Ease of manufacture
If components are mounted as individual components on a printed circuit board, then ease of manufacture and assembly is improved, but interconnection length increases leading to higher switching losses and parasitic inductances
Solution Approach 1:
By integrating all components and interconnections within a single package, the patent eliminates long external traces and reduces the number of solder joints on the printed circuit board. The short internal interconnections between components on the carrier minimize parasitic inductances and resistance, thereby reducing switching losses while maintaining assembly efficiency through standardized package fabrication.
3Loss of energy
If semiconductor chip packages are integrated to reduce switching losses and parasitic inductances, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The patent segments the integrated package into distinct functional modules: semiconductor chips for power conversion, driver chips for control, passive components for filtering and decoupling, and a carrier for mechanical support and thermal management. This modular segmentation allows each component to be optimized independently while simplifying the overall integration process through standardized mounting and interconnection techniques.
Solution Approach 2:
The carrier serves multiple functions simultaneously: it provides mechanical support for mounting components, establishes electrical connections through metallization layers and via holes, facilitates thermal conduction from heat-generating components, and enables compact three-dimensional arrangement. This multi-functionality reduces the need for separate structural elements, thereby managing complexity while achieving integration benefits.
4Productivity
If multiple semiconductor chips and driver chips are integrated within a package, then interconnect efficiency is improved, but thermal management challenges increase
Solution Approach 1:
The patent implements localized thermal management by attaching heat sinks or thermally conductive materials directly to heat-generating semiconductor chips on the carrier. The carrier itself is designed with thermally conductive pathways that channel heat from multiple components to designated heat dissipation areas. This localized approach efficiently manages heat at the source while maintaining high interconnect efficiency through short internal connections.
Data Source
AI summary
A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.