Semiconductor Chip Package Molding Layer for Solder Joint Reliability
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Solution Overview
Problem
Semiconductor packages, such as FBGA and CSP, face challenges in reliability and cost due to high processing costs and limitations in downsizing solder ball layouts, while wafer-level CSPs struggle with solder joint reliability as chip sizes decrease.
Innovation Solution
A semiconductor chip package design featuring a molding extension part surrounding the chip, redistribution patterns extending to these areas, bump solder balls on the patterns, and a molding layer covering the chip while exposing portions of the solder balls with concave meniscus surfaces, enhancing solder joint reliability and thermal stress dispersion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If solder ball size is scaled down to match smaller semiconductor chips, then chip size is reduced, but solder joint reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating a molding layer with non-uniform thickness around the solder balls. The molding layer has greater thickness at the bottom and sides of each solder ball, providing enhanced local support and stress distribution exactly where needed for small solder balls, while maintaining the overall miniaturization of the chip package.
Solution Approach 2:
The patent changes the physical parameters of the molding layer, specifically its thickness distribution and material composition. By controlling the molding layer to have variable thickness (thicker at bottom and sides) and using specific material properties, the patent compensates for the reduced size of solder balls, maintaining their mechanical strength and joint reliability despite miniaturization.
2Ease of manufacture
If conventional molding structures are used with small solder balls, then manufacturing is simple, but solder ball adhesion and thermal stress resistance are insufficient
Solution Approach 1:
The patent implements local quality by creating a molding layer with spatially varying thickness that provides enhanced support specifically at critical locations (bottom and sides of solder balls) while maintaining uniform processing. This localized structural optimization improves adhesion and thermal stress resistance without complicating the overall molding process.
3Ease of manufacture
If uniform molding layer thickness is used, then manufacturing is easier, but thermal stress concentration occurs at solder ball interfaces
Solution Approach 1:
The patent changes the thickness parameter of the molding layer from uniform to non-uniform distribution. The molding layer is designed to be thicker at the bottom and lateral sides of each solder ball, which provides better thermal stress distribution and reduces stress concentration at the solder ball interfaces, while still using standard molding processes.
Data Source
AI summary
A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.