Semiconductor Chip Pads for Power Supply and Noise Reduction
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Solution Overview
Problem
Semiconductor chips face challenges in balancing power supply and signal transmission while minimizing chip size, as increasing the number of power pads can lead to increased chip size and simultaneous switching noise (SSN), and reducing them can exacerbate SSN.
Innovation Solution
The semiconductor chip design includes additional pads for ground and power supply voltages, integrated conductive rings, and input/output buffers, allowing for efficient power distribution and signal transmission without increasing chip size by strategically placing these elements on the chip surface and within the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of power pads is increased, then power supply capability is improved, but chip size increases
Solution Approach 1:
The patent combines power pads and ground pads into integrated power supply units, where each unit contains both a power pad and a ground pad. This merging allows the chip to achieve sufficient power supply capability while reducing the total number of discrete pads required, thereby minimizing chip size without compromising power delivery.
Solution Approach 2:
The power supply units are designed to serve multiple functions: they provide power supply, establish ground references, and enable signal transmission. By making these units multi-functional, the chip reduces the need for separate dedicated pads for each function, thus improving power supply capability while keeping the chip size compact.
2Area of stationary object
If the number of power pads is reduced, then chip size is minimized, but simultaneous switching noise increases
Solution Approach 1:
By merging power pads and ground pads into integrated units with proper spatial arrangement, the patent creates localized power supply domains that reduce ground bounce and simultaneous switching noise. The close proximity of power and ground pads in each unit provides low-impedance return paths, effectively suppressing noise while maintaining a compact chip size.
Solution Approach 2:
The patent implements local quality by ensuring that each power supply unit has its own dedicated ground pad positioned adjacent to the power pad. This local pairing creates low-impedance current loops that minimize electromagnetic interference and simultaneous switching noise, allowing the chip to maintain small size without suffering from noise issues.
3Power
If additional pads are integrated into existing input/output units, then power supply efficiency is improved, but pad arrangement complexity increases
Solution Approach 1:
The patent segments the chip surface into multiple discrete power supply units, each with a standardized configuration of power pads and ground pads. This segmentation approach simplifies the overall pad arrangement by providing a modular, repeatable pattern that improves power supply efficiency while making the design more manageable despite the increased functional integration.
Data Source
AI summary
A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.