Semiconductor Chip Protrusion Alignment for SiP Warpage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor devices with a system in package (SiP) structure, bonding failures at micro-bumps occur due to warpage and alignment issues during the electrical connection of semiconductor chips, leading to connectivity problems and potential short-circuits.

Innovation Solution

The method involves forming protrusions on the semiconductor chips to maintain alignment and strength before bonding, using a thermosetting resin for the protrusions, and performing a reflow process followed by curing to secure the connections, thereby reducing warpage and enhancing the reliability of the bump connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor chips are electrically connected using micro-bumps, then electrical signal transmission between chips is achieved, but bonding failures occur due to warpage and alignment issues

Engineering Contradiction:
Improvebonding reliabilityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming protrusions on the semiconductor chip surfaces before the electrical connection process. These protrusions are created in advance to maintain proper alignment and spacing between chips during subsequent bonding operations, preventing alignment issues that lead to bonding failures.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces protrusions as intermediary structures between the semiconductor chips and micro-bumps. These protrusions serve as mediators that maintain alignment and spacing, reducing warpage effects and preventing direct contact issues between chips and bumps, thereby improving bonding reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Strength

If high-temperature reflow process is used for electrical connection, then solder bonding is achieved, but warpage increases causing alignment issues

Engineering Contradiction:
Improveconnection strengthVSAvoidchip warpage
Core Design Contradiction:
StrengthVSShape

Solution Approach 1:

The protrusions are formed before the high-temperature reflow process to pre-establish the correct spatial relationship between chips. This preliminary structuring compensates for expected warpage during heating, maintaining alignment precision even as the chips undergo thermal expansion and deformation during solder bonding.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The protrusions act as beforehand cushioning elements that absorb and compensate for warpage effects during the reflow process. By providing a pre-formed structural framework, they cushion against the dimensional changes and misalignments that occur when chips are heated to solder melting temperatures.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses bonding failures and improves the connection strength and reliability of micro-bumps between semiconductor chips, reducing the risk of warpage-induced fractures and ensuring reliable electrical signal transmission.

Implementation Method 1

curing the protrusion at a temperature that is lower than a melting point temperature of metals contained in the first electrode and the second electrode after electrically connecting the first semiconductor chip and the second semiconductor chip

Methodology Applied
Scientific EffectCuring:

Implementation Method 2

electrically connecting the first semiconductor chip and the second semiconductor chip at temperature that is higher than a melting point temperature of at least a part of the metals contained in the first electrode and the second electrode

Methodology Applied
Scientific EffectMelting: Melting

Data Source

PatentUS9570414B2Semiconductor device and method of manufacturing the semiconductor device
Publication Date: 2017.02.14 KIOXIA CORP
  • US9570414B2 patent drawing
  • US9570414B2 patent drawing
  • US9570414B2 patent drawing

AI summary

According to one embodiment, a first electrode is formed on a first face of a first semiconductor chip, and a second electrode and a protrusion are formed on a second face of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are spaced from one another by the protrusion in such a manner that the first face and the second face face each other. The first semiconductor chip and the second semiconductor chip are subject to reflow to be electrically connected to each other, and then the protrusion is cured at a temperature lower than a reflow temperature.