Semiconductor Chip Power Distribution via RDL and Conductive Member
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Solution Overview
Problem
Semiconductor chip packaging faces challenges in reducing localized voltage drops, which can lead to defective operation, especially in circuits operating at low voltages, due to internal resistance in power distribution structures.
Innovation Solution
The solution involves forming at least two potential equivalent metal traces in a semiconductor chip's metal interconnection level, with a passivation layer and a redistribution layer (RDL) that electrically connects these traces through a conductive member, reducing resistance and voltage drops. This configuration is compatible with conventional manufacturing standards and can be applied to various packaging types, including PBGA packages with metal heat spreaders.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If thin metal wires are used for power distribution, then device size is reduced, but voltage drop increases
Solution Approach 1:
The patent introduces a vertical dimension by stacking multiple power distribution layers (first and second power distribution layers) to create three-dimensional power paths. This allows power to be distributed through multiple levels rather than relying solely on thin planar wires, reducing resistance and voltage drop while maintaining compact footprint.
Solution Approach 2:
The patent combines multiple power distribution layers with conductive plugs extending vertically between them, creating integrated three-dimensional power networks. This merging of horizontal and vertical conductive paths provides redundant power routes and reduces overall resistance, addressing the voltage drop issue without increasing device footprint.
2Reliability
If power distribution routing is increased to reduce voltage drop, then voltage stability improves, but device complexity increases
Solution Approach 1:
The patent segments the power distribution system into multiple discrete layers and regions, with each layer handling specific power routing functions. This segmentation allows independent optimization of each layer's routing paths and enables modular design, improving voltage stability without proportionally increasing overall complexity.
Solution Approach 2:
The patent implements different conductor configurations and materials in different regions and layers of the power distribution system. By tailoring the conductive properties locally to specific power density requirements, the design achieves improved voltage stability in critical areas without unnecessarily complicating the entire power distribution network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces localized voltage drops, enhances thermal and electrical performance, and provides a flexible, cost-effective solution that does not require redesigning the substrate, improving the overall performance and reliability of semiconductor chip packaging.
Implementation Method 1
a conductive member externally mounted on the passivation layer between the two openings... the potential equivalent metal traces are electrically connected to each other through the RDL and the conductive member
Data Source
AI summary
A semiconductor chip includes a die mounted on a packaging substrate. The die includes a semiconductor substrate; inter-metal dielectric layers on the semiconductor substrate; levels of metal interconnection, wherein at least two potential equivalent metal traces are formed in a level of the metal interconnection; a passivation layer disposed over the two metal traces, wherein two openings are formed in the passivation layer to expose portions of the two metal traces; a conductive member externally mounted on the passivation layer between the two openings; and a redistribution layer formed over the conductive member.