Semiconductor Chip Reinforcing Power Pad Placement

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Solution Overview

Problem

The increasing number of external connecting pads on semiconductor chips due to larger integrated circuits leads to increased area and fabrication challenges, particularly with staggered bonding pad arrangements causing dead space that is not effectively utilized.

Innovation Solution

Incorporating a reinforcing power supply pad placed between I/O cell rows, connected to cell connecting pads but not directly to I/O cells, to provide additional power supply without area expansion, reducing inductance and impedance, and allowing for fewer power supply cells and pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding pads are arranged in a staggered pattern to prevent shorting, then reliability is improved, but area is increased due to dead space between I/O cell rows

Engineering Contradiction:

Improvebonding pad shorting preventionVSAvoidsemiconductor chip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent converts the harmful dead space between I/O cell rows into a beneficial location for placing reinforcing power supply pads. By positioning these pads in the previously wasted space, the invention reduces overall chip area while maintaining the staggered bonding pad arrangement that prevents shorting.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The region between I/O cell rows, which originally served only as spacing to prevent bonding wire shorting, is given an additional function by placing reinforcing power supply pads there. This multi-functional use of space reduces the total chip area required.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the number of external connecting pads is increased to support larger integrated circuits, then functionality is improved, but area is increased

Engineering Contradiction:

Improvenumber of external connecting padsVSAvoidsemiconductor chip area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension (space between I/O cell rows) rather than only horizontal expansion to accommodate additional pads. By placing reinforcing power supply pads in the inter-row space, the design supports increased functionality without proportional area increase.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If I/O cell rows are separated by a predetermined distance to prevent bonding wire shorting, then reliability is improved, but dead space is created that increases area

Engineering Contradiction:

Improvebonding wire shorting preventionVSAvoiddead space area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transforms the dead space created by necessary I/O cell row separation into a useful location for reinforcing power supply pads. This maintains the reliability benefit of separation while eliminating the area waste.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11621259B2Semiconductor chip

Publication Date: 2023.04.04 SOCIONEXT INC

AI summary

A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.